专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20090134937A1 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US20090134937A1
公开(公告)日：2009-05-28
申请号：US12287620
申请日：2008-10-10
申请人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
发明人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
IPC分类号： G05F1/10
CPC分类号： G11C5/145
摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.
摘要翻译：电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

52. 发明授权

US07349268B2 Voltage generation circuit and semiconductor memory device including the same 有权
标题翻译：电压产生电路和包括其的半导体存储器件
公开(公告)号：US07349268B2
公开(公告)日：2008-03-25
申请号：US11293890
申请日：2005-12-02
申请人： Hyong-Ryol Hwang , Young-Hyun Jun
发明人： Hyong-Ryol Hwang , Young-Hyun Jun
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要翻译：提供了包括该电压产生电路和半导体存储器件的电压产生电路。电压产生电路包括：电压电平检测器，其检测第一高电平的电平以产生第一高电压电平检测信号，并检测第二高电平的电平以产生第二高电压电平检测信号; 控制信号发生器，当所述第一高电压电平检测信号有效时，依次产生至少四个泵送控制信号，当所述第一高电压电平检测信号无效时产生控制信号，并且产生至少四个泵送控制信号响应于电源电压的电平; 以及电压发生器，其响应于所述至少四个泵送控制信号泵送升压节点以产生所述第一高电压，并且响应于所述控制信号将电压从所述升压节点传输到第二高电压发生端子，以产生所述第二高电压高压。

53. 发明申请

US20060250861A1 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US20060250861A1
公开(公告)日：2006-11-09
申请号：US11416077
申请日：2006-05-03
申请人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

54. 发明授权

US06813204B2 Semiconductor memory device comprising circuit for precharging data line 有权
标题翻译：半导体存储器件包括用于预充电数据线的电路
公开(公告)号：US06813204B2
公开(公告)日：2004-11-02
申请号：US10324406
申请日：2002-12-20
申请人： Chul-soo Kim , Young-hyun Jun , Jae-goo Lee
发明人： Chul-soo Kim , Young-hyun Jun , Jae-goo Lee
IPC分类号： G11C700
CPC分类号： G11C7/1084 , G11C7/1048
摘要： A semiconductor memory device having a circuit precharging a data line comprises a first precharge circuit, which precharges a first data line pair to a first voltage level in a precharge operation state, and a second precharge circuit, which precharges a second data line pair to a second voltage level in a precharge operation state. The semiconductor memory device comprises a data input driver, which receives data and drives the data to the first data line pair, a switch, which in response to a selection signal, connects or disconnects the first data line pair with the second data line pair, and a charge-sharing control circuit, which in response to the selection signal makes one line of the first data line pair and one line of the second data line pair share charge. The semiconductor memory device reduces current consumption over repeated write/precharge operations.
摘要翻译：具有对数据线进行预充电的电路的半导体存储器件包括：第一预充电电路，其将第一数据线对预充电到预充电操作状态下的第一电压电平;以及第二预充电电路，其将第二数据线对预充电到在预充电操作状态下的第二电压电平。半导体存储器件包括数据输入驱动器，其接收数据并将数据驱动到第一数据线对;开关，其响应于选择信号将第一数据线对与第二数据线对连接或断开，以及电荷共享控制电路，其响应于选择信号使得第一数据线对的一条线和第二数据线对的一条线共享电荷。半导体存储器件通过重复的写入/预充电操作来减少电流消耗。

55. 发明授权

US06667895B2 Integrated circuit device and module with integrated circuits 失效
公开(公告)号：US06667895B2
公开(公告)日：2003-12-23
申请号：US10192901
申请日：2002-07-10
申请人： Seong-Jin Jang , Young-Hyun Jun , Chang-Man Khang
发明人： Seong-Jin Jang , Young-Hyun Jun , Chang-Man Khang
IPC分类号： G11C506
CPC分类号： G11C5/063 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

56. 发明授权

US06294950B1 Charge pump circuit having variable oscillation period 有权
标题翻译：电荷泵电路具有可变的振荡周期
公开(公告)号：US06294950B1
公开(公告)日：2001-09-25
申请号：US09472163
申请日：1999-12-27
申请人： Jae-Goo Lee , Young-Hyun Jun
发明人： Jae-Goo Lee , Young-Hyun Jun
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2001/0032 , Y02B70/16
摘要： The present invention relates to a charge pump circuit which can vary an oscillation frequency for charge pumping in proportion to a charge consumption amount. The charge pump circuit includes: a voltage divider dividing a boosting voltage to a predetermined level; a voltage level sensing unit sensing a voltage difference between a divided voltage outputted from the voltage divider and a reference voltage, and outputting a control voltage corresponding to the sensed voltage difference; an oscillator circuit varying an oscillation frequency in accordance with the control voltage outputted from the voltage level sensing unit; and a charge pump performing a pumping operation in accordance with the output from the oscillator circuit, and outputting a boosting voltage.
摘要翻译：电荷泵电路技术领域本发明涉及一种电荷泵电路，其可以根据电荷消耗量来改变电荷泵送的振荡频率。电荷泵电路包括：将升压电压分压到预定电平的分压器; 电压电平感测单元，感测从分压器输出的分压电压与参考电压之间的电压差，并输出与感测的电压差对应的控制电压; 振荡器电路，根据从电压电平检测单元输出的控制电压来改变振荡频率; 以及电荷泵，根据振荡电路的输出进行泵浦动作，并输出升压电压。

57. 发明授权

US6031402A Clock synchronizing circuit with power save mode 失效
标题翻译：具有省电模式的时钟同步电路
公开(公告)号：US6031402A
公开(公告)日：2000-02-29
申请号：US974382
申请日：1997-11-19
申请人： Sung Ho Wang , Young-Hyun Jun
发明人： Sung Ho Wang , Young-Hyun Jun
IPC分类号： G06F1/12 , H03K19/00 , H03L7/08 , H03L7/081 , H03L7/087 , H04L25/40 , H03L7/06
CPC分类号： H03L7/0812 , H03L7/0802 , H03L7/087
摘要： A clock synchronizing circuit provides reduced power consumption. A first phase comparator compares an external clock signal delayed for a predetermined time with a feedback clock signal to detect their phase error, and a second phase comparator compares an external clock signal with a feedback clock signal delayed for a predetermined time to detect their phase error. A charge pump changes a charge amount depending on phase error detecting signals from the first and second phase error comparators, and a phase compensator compensates the phase of the external clock signal depending on the charge amount from the charge pump. A controller controls the overall system or some portion thereof to be converted to a power save mode if the phase of the external clock signal is synchronized with that of the feedback clock signal by the phase compensator.
摘要翻译：时钟同步电路提供降低的功耗。第一相位比较器将延迟预定时间的外部时钟信号与反馈时钟信号进行比较，以检测它们的相位误差，第二相位比较器将外部时钟信号与延迟预定时间的反馈时钟信号进行比较，以检测它们的相位误差。电荷泵根据来自第一和第二相位误差比较器的相位误差检测信号改变电荷量，相位补偿器根据来自电荷泵的电荷量来补偿外部时钟信号的相位。如果外部时钟信号的相位与相位补偿器的反相时钟信号的相位同步，则控制器控制整个系统或其某些部分被转换成省电模式。

58. 发明授权

US5905402A Voltage pump circuit having an independent well-bias voltage 失效
标题翻译：电压泵电路具有独立的良好偏置电压
公开(公告)号：US5905402A
公开(公告)日：1999-05-18
申请号：US866128
申请日：1997-05-30
申请人： Tae-Hoon Kim , Young-Hyun Jun
发明人： Tae-Hoon Kim , Young-Hyun Jun
IPC分类号： G11C11/407 , G11C5/14 , G11C11/408 , H01L21/8234 , H01L27/088 , H02M3/07 , G05F3/02
CPC分类号： H02M3/07
摘要： A voltage pump circuit for precharging/pumping a charge to/from a pumping capacitor separately employs a voltage generator for independently supplying a well-bias voltage to a PMOS transfer transistor which transfers a charge of a precharged capacitor to produce reference voltage. The voltage of the voltage generator is applied to a well of the PMOS transfer transistor to body bias the PMOS transfer transistor and, thus, ruggedize its threshold voltage transistor. Here, the well-bias voltage equals or exceeds the reference voltage while being approximately twice a power source voltage. The well-bias voltage generator includes a non-overlap control circuit for receiving a pulse signal as an input to generate two pulse signals having different points of changing into high and low states, a second pumping capacitor, first, second and third bootstrap capacitors, a precharge circuit for precharging the voltage on the second pumping capacitor and first and second bootstrap capacitors for a predetermined period, a first step control circuit for controlling a first-step transistor, a second step control circuit for controlling a second-step transistor and a pumping control circuit for controlling a third-step transistor, which are provided for precharging the voltage to the third bootstrap capacitor, and a transfer transistor having a gate connected to the reference voltage of the third bootstrap capacitor for transferring the well-bias voltage.
摘要翻译：用于向/从泵送电容器预充电/泵送电荷的电压泵电路分别采用电压发生器，用于独立向PMOS传输晶体管提供阱偏置电压，PMOS传输晶体管传送预充电电容器的电荷以产生参考电压。电压发生器的电压被施加到PMOS传输晶体管的阱以对PMOS传输晶体管进行偏置，并因此加强其阈值电压晶体管。这里，阱偏置电压等于或超过参考电压，而大约是电源电压的两倍。阱偏置电压发生器包括：不重叠控制电路，用于接收作为输入的脉冲信号，以产生具有变为高和低状态的不同点的两个脉冲信号;第二泵浦电容器，第一，第二和第三自举电容器; 预充电电路，用于对预定时间段内的第二泵浦电容器和第一和第二自举电容器进行预充电;第一级控制电路，用于控制第一级晶体管;第二级控制电路，用于控制第二级晶体管;以及泵控制电路，用于控制用于对第三自举电容器进行电压预充电的第三级晶体管;以及传输晶体管，其具有连接到第三自举电容器的参考电压的栅极，用于传送阱偏置电压。

59. 发明授权

US5602506A Back bias voltage generator 失效
标题翻译：背偏置电压发生器
公开(公告)号：US5602506A
公开(公告)日：1997-02-11
申请号：US362299
申请日：1994-12-22
申请人： Tae-Hoon Kim , Young-Hyun Jun
发明人： Tae-Hoon Kim , Young-Hyun Jun
IPC分类号： H01L27/04 , G11C5/14 , G11C11/408 , H01L21/822 , H02M3/07 , G05F1/10
CPC分类号： G11C5/146 , H02M3/07 , H01L2924/0002
摘要： A back bias voltage generator comprising a power-on signal generator for generating a power-on signal when an external voltage remains at a constant level, a reference voltage generator for generating a reference voltage in response to the power-on signal from the power-on signal generator, an internal voltage generator for generating an internal voltage and an internal/external voltage select signal in response to the reference voltage from the reference voltage generator, the internal voltage being constant in level, a back bias voltage sensor for generating an oscillation enable signal in response to the external voltage or the internal voltage from the internal voltage generator under control of the internal/external voltage select signal from the internal voltage generator, an oscillator for generating an oscillating signal at a desired period and an enable signal in response to the oscillation enable signal from the back bias voltage sensor and outputting the generated enable signal to the internal voltage generator, and a back bias voltage pump for performing a voltage pumping operation in response to the oscillating signal from the oscillator to generate a desired level of back bias voltage and outputting the generated back bias voltage to an external circuit and the back bias voltage sensor.
摘要翻译：背偏置电压发生器，其包括用于当外部电压保持在恒定电平时产生通电信号的上电信号发生器，用于响应于来自电源开关信号的电源接通信号产生参考电压的参考电压发生器，信号发生器，内部电压发生器，用于响应于来自参考电压发生器的参考电压产生内部电压和内部/外部电压选择信号，内部电压水平恒定;用于产生振荡的反向偏置电压传感器在来自内部电压发生器的内部/外部电压选择信号的控制下，响应于来自内部电压发生器的外部电压或内部电压的使能信号，用于在期望周期产生振荡信号的振荡器和响应中的使能信号到来自背偏压电压传感器的振荡使能信号，并输出所产生的使能信号内部电压发生器和反向偏置电压泵，用于响应于来自振荡器的振荡信号进行电压抽运操作，以产生期望电平的反向偏置电压，并将产生的反向偏置电压输出到外部电路，并且背偏置电压传感器。

60. 发明授权

US08638621B2 Semiconductor memory device having a hierarchical bit line scheme 有权
标题翻译：具有分层位线方案的半导体存储器件
公开(公告)号：US08638621B2
公开(公告)日：2014-01-28
申请号：US13413938
申请日：2012-03-07
申请人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
发明人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
IPC分类号： G11C7/00 , G11C11/419
CPC分类号： G11C11/419 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.
摘要翻译：一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式