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    • 51. 发明授权
    • Protecting ownership transfer with non-uniform protection windows
    • 用不均匀的保护窗保护所有权转让
    • US07734876B2
    • 2010-06-08
    • US11560603
    • 2006-11-16
    • James S. Fields, Jr.Benjiman L. GoodmanGuy L. GuthrieWilliam J. StarkeJeffrey A. Stuecheli
    • James S. Fields, Jr.Benjiman L. GoodmanGuy L. GuthrieWilliam J. StarkeJeffrey A. Stuecheli
    • G06F13/00
    • G06F12/0833
    • In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Within data storage in the data processing system, a data structure indicates a duration of a protection window extension for each of the plurality of agents. Each protection window extension is a period following receipt of a combined response during which an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. Each of the plurality of agents is configured with a duration of a protection window extension by reference to the data structure, and at least two of the agents have protection window extensions of differing durations. The plurality of agents thereafter employ the configured protection window extensions.
    • 在数据处理系统中,多个代理之间进行通信。 每个操作包括一个请求和组合的响应,代表对该请求的全系统响应。 在数据处理系统中的数据存储中,数据结构指示多个代理中的每一个的保护窗口扩展的持续时间。 每个保护窗口扩展是接收到组合响应之后的周期,在该周期期间,所述多个代理中的相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。 通过参考数据结构,多个代理中的每一个配置有保护窗口扩展的持续时间,并且至少两个代理具有不同持续时间的保护窗口扩展。 此后,多个代理程序采用配置的保护窗口扩展。
    • 52. 发明授权
    • Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains
    • 数据处理系统,缓存系统和用于处理具有多个相干域的数据处理系统中的刷新操作的方法
    • US07543116B2
    • 2009-06-02
    • US11342951
    • 2006-01-30
    • Guy L. GuthrieJohn T. Hollaway, Jr.William J. StarkeDerek E. Williams
    • Guy L. GuthrieJohn T. Hollaway, Jr.William J. StarkeDerek E. Williams
    • G06F12/00
    • G06F12/0822G06F12/0804G06F12/0831
    • A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator indicating whether the target memory block is cached outside the first coherency domain. During operation, the first coherency domain receives a flush operation broadcast to the first and second coherency domains, where the flush operation specifies the target address of the target memory block. The first coherency domain also receives a combined response for the flush operation representing a system-wide response to the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system. In response to a determination that the combined response indicates that a cached copy of the target memory block may remain in the data processing system, the domain indicator is updated to indicate that the target memory block is cached outside of the first coherency domain.
    • 缓存相干数据处理系统至少包括第一和第二相干域。 第一相干域包括存储器控制器,具有由目标地址标识的目标存储器块的相关系统存储器,以及指示目标存储器块是否被高速缓存在第一相干域之外的域指示符。 在操作期间,第一相干域接收向第一和第二相干域广播的刷新操作,其中刷新操作指定目标存储器块的目标地址。 第一个相干域还接收表示对刷新操作的系统范围响应的刷新操作的组合响应。 响应于在组合响应的第一相关域中的接收,确定组合响应是否指示目标存储器块的高速缓存副本可能保留在数据处理系统内。 响应于确定组合响应指示目标存储器块的高速缓存副本可能保留在数据处理系统中,则域指示符被更新以指示目标存储器块被高速缓存在第一相干域之外。
    • 53. 发明授权
    • Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains
    • 处理器,数据处理系统和用于初始化具有多个相干域的数据处理系统中的存储器块的方法
    • US07475196B2
    • 2009-01-06
    • US11388001
    • 2006-03-23
    • Ravi K. ArimilliGuy L. GuthrieWilliam J. StarkeDerek E. Williams
    • Ravi K. ArimilliGuy L. GuthrieWilliam J. StarkeDerek E. Williams
    • G06F13/00
    • G06F12/0822G06F12/084
    • A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.
    • 数据处理系统至少包括第一和第二相干域,每个域包括至少一个处理器核和存储器。 响应于指示要初始化的目标存储器块的处理器核心的初始化操作,第一相干域中的高速缓冲存储器确定目标存储器块相对于高速缓存存储器的一致性状态。 响应于该确定,高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。 响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围,并且响应于确定第一相关性域的第一相关性域和第二相关域 第二一致性状态。 然后,高速缓冲存储器播放具有所选范围的初始化请求。 响应于初始化请求,将目标存储器块在数据处理系统的存储器内初始化为初始化值。
    • 56. 发明授权
    • Data processing system, cache system and method for updating an invalid coherency state in response to snooping an operation
    • 数据处理系统,缓存系统和用于响应于窥探操作来更新无效一致性状态的方法
    • US07451277B2
    • 2008-11-11
    • US11388017
    • 2006-03-23
    • Guy L. GuthrieWilliam J. StarkeJeffrey A. StuecheliDerek E. Williams
    • Guy L. GuthrieWilliam J. StarkeJeffrey A. StuecheliDerek E. Williams
    • G06F12/00
    • G06F12/0831G06F2212/507
    • A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requester that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.
    • 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中,将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态, 存储位置不包含有效数据。 响应于窥探独占访问操作,专用访问请求指定与地址标签匹配的目标地址,并且指示发起独占访问操作的请求者的相对域位置,第一高速缓存存储器从第一数据更新相关性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态,存储位置不包含有效数据,以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内 基于请求者的相对位置成功完成独占访问操作。
    • 57. 发明授权
    • Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule
    • 数据处理系统,处理器和数据处理方法,其中本地存储器访问请求以固定的时间表被服务
    • US07447844B2
    • 2008-11-04
    • US11457322
    • 2006-07-13
    • Leo J. ClarkGuy L. GuthrieWilliam J. StarkeDerek E. Williams
    • Leo J. ClarkGuy L. GuthrieWilliam J. StarkeDerek E. Williams
    • G06F12/00
    • G06F12/1425G06F12/0817G06F12/0897
    • A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
    • 处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列,数据阵列的内容目录。 缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机,通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器,地址冲突逻辑 其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。 调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务,并且向仲裁器发出信号,以根据固定的时间表对第二组中的存储器访问请求进行直接服务。
    • 59. 发明申请
    • DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC SUPPORTING MULTIPLE PLANES OF PROCESSING NODES
    • 数据处理系统,方法和互连织物支持多个加工点的平面
    • US20080225863A1
    • 2008-09-18
    • US12124639
    • 2008-05-21
    • Ravi K. ArimilliBenjiman L. GoodmanGuy L. GuthriePraveen S. ReddyWilliam J. Starke
    • Ravi K. ArimilliBenjiman L. GoodmanGuy L. GuthriePraveen S. ReddyWilliam J. Starke
    • H04L12/56
    • G06F15/16
    • A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.
    • 数据处理系统包括包括第一多个处理节点的第一平面,每个处理节点包括多个处理单元,以及包括第二多个处理节点的第二平面,每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路,其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元,用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元,所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元, 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。