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    • 54. 发明申请
    • GENERATION OF A PULSED JET BY JET VECTORING THROUGH A NOZZLE WITH MULTIPLE OUTLETS
    • 喷射喷嘴通过具有多个出口的喷嘴引起的脉冲喷射的产生
    • US20150315998A1
    • 2015-11-05
    • US14796772
    • 2015-07-10
    • Southern Methodist University
    • Paul S. Krueger
    • F02K1/00F02K9/82F15D1/08F02K9/28
    • A method of producing a pulsatile jet flow from a substantially constant flow primary jet in a way that is mechanically efficient, easy to implement, and allows direct control over pulse duration and pulsing frequency is disclosed herein. The invention includes at least two components: (a) a constant flow fluid jet produced by any normal method (e.g., propeller) that can be directionally vectored fluidically, mechanically, or electromagnetically and (b) a nozzle with multiple outlets (orifices) through which the vectored jet may be directed. By alternately vectoring the jet through different outlets, a transient (pulsatile) flow at an outlet is obtained even with a substantially constant primary jet flow. Additionally, the nozzle outlets may be oriented in different directions to provide thrust vectoring, making the invention useful for maneuvering, directional control, etc.
    • 本文公开了以机械效率,易于实施并且允许对脉冲持续时间和脉冲频率的直接控制的方式从基本上恒定的流量初级射流产生脉冲喷射流的方法。 本发明包括至少两个部件:(a)通过任何常规方法(例如,螺旋桨)产生的恒定流动流体射流,其可以流体地,机械地或电磁地定向向量,以及(b)具有多个出口(孔口)通过的喷嘴 向导可以被引导。 通过交替地通过不同的出口引导射流,即使以基本上恒定的一次喷射流也可以获得出口处的瞬时(脉动)流动。 此外,喷嘴出口可以沿不同方向定向以提供推力矢量化,使得本发明可用于操纵,方向控制等。
    • 55. 发明授权
    • Single clock distribution network for multi-phase clock integrated circuits
    • 单时钟分配网络用于多相时钟集成电路
    • US08847625B2
    • 2014-09-30
    • US13769313
    • 2013-02-16
    • Southern Methodist University
    • Mitchell Aaron ThorntonRohit Menon
    • H03K19/00H03L7/00G06F1/04G06F1/10H03K19/096
    • H03K19/096G06F1/10
    • A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.
    • 多值逻辑(MVL)电路包括产生具有三个或更多个第三MVL电平的MVL时钟信号的MVL时钟发生器,连接到MVL时钟发生器的单个MVL时钟信号分配网络,以及三个或更多个第一MVL选择电路 连接到单个MVL时钟信号分配网络,其中i = 0到N,N> = 3。 每个第i个MVL选择电路对应于指定的第i个MVL电平。 第i个MVL选择电路输出第i个二进制时钟信号,该信号具有:(a)每当MVL时钟信号等于第i个MVL电平并且第i个数据输入接收第一逻辑电平时,第一逻辑电平,(b)第二逻辑电平 每当MVL时钟信号等于第i个MVL电平并且第i个数据输入接收第二逻辑电平时,以及(c)每当MVL时钟信号不等于第i个MVL电平时,第i个二进制时钟信号的先前逻辑电平 。
    • 57. 发明申请
    • Look-Up-Table Digital Predistortion Technique for High-Voltage Power Amplifiers in Ultrasonic Applications
    • 超声波应用中高压功率放大器的查找表数字预失真技术
    • US20130162349A1
    • 2013-06-27
    • US13724615
    • 2012-12-21
    • Southern Methodist University
    • Zheng GaoPing Gui
    • H03G1/00
    • H03G1/0005H03F1/3241
    • The present invention includes a digital controller for use with an ultrasound power amplifier circuit to increase linearity and efficiency of the ultrasound power amplifier circuit. The digital controller includes a digital signal generator and a memory unit that is coupled to the digital signal generator. The memory unit includes a processor that obtains an output signal from the ultrasound power amplifier circuit, calculates error by obtaining a difference between an ideal output signal and the output signal that is obtained from the ultrasound power amplifier circuit, and equalizes an input signal from the digital signal generator to reduce nonlinearity in the output signal of the ultrasound power amplifier circuit. The memory unit includes a look-up-table for storing values of error.
    • 本发明包括一个与超声波功率放大器电路一起使用以提高超声功率放大器电路的线性度和效率的数字控制器。 数字控制器包括数字信号发生器和耦合到数字信号发生器的存储器单元。 存储单元包括从超声波功率放大器电路获得输出信号的处理器,通过获得从超声波功率放大器电路获得的理想输出信号和输出信号之间的差来计算误差,并且将来自 数字信号发生器,以减少超声波功率放大器电路输出信号的非线性。 存储单元包括用于存储错误值的查找表。