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51. 发明授权

US08344472B2 Semiconductor device and method 有权
标题翻译：半导体器件及方法
公开(公告)号：US08344472B2
公开(公告)日：2013-01-01
申请号：US12750151
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
发明人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
IPC分类号： H01L29/66
CPC分类号： H01L27/098 , H01L27/0705 , H01L27/085 , H01L27/088 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80′) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80′) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801′, 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70′, 90, 90′) by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.
摘要翻译：使用浮置掩埋层的晶体管（21,41）可能易于与浮动掩埋层的噪声耦合。在IGFETS中，通过提供耦合埋层（102,142,172,202）和IGFET源（22,42）或漏极（24,44）的常开开关（80,80'）来减少或消除这种情况。当晶体管（71,91）为OFF时，这夹着埋层电压并且基本上防止与其耦合的噪声。当漏极 - 源极电压V DS超过开关（80,80'）阈值电压Vt时，它变为OFF，允许埋层（102,142,172,202）浮起，从而恢复正常的晶体管作用而不降低击穿电压或导通电阻。在优选实施例中，正向导通的横向JFET（801,801'，801-1,801-2,801-3）方便地提供该开关功能。横向JFET（801-3）可以通过掩模改变而被包括在设备（70,70'，90,90'）中，而不需要添加或定制任何工艺步骤，从而提供改进的抗噪声性，而不会显着增加制造成本。该改进适用于P（90-1）和N通道（70-1,70-2,70-3）晶体管，并且对于LDMOS器件特别有用。

52. 发明授权

US08338872B2 Electronic device with capcitively coupled floating buried layer 有权
标题翻译：具有电容耦合浮动掩埋层的电子器件
公开(公告)号：US08338872B2
公开(公告)日：2012-12-25
申请号：US12750166
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Ronghua Zhu , Weixiao Huang , Bernhard H. Grote
发明人： Vishnu K. Khemka , Tahir A. Khan , Ronghua Zhu , Weixiao Huang , Bernhard H. Grote
IPC分类号： H01L29/66 , H01L21/00 , H01L21/84
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译：使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。该改进对于LDMOS器件特别有用。

53. 发明授权

US08330220B2 LDMOS with enhanced safe operating area (SOA) and method therefor 有权
标题翻译： LDMOS具有增强的安全操作区（SOA）及其方法
公开(公告)号：US08330220B2
公开(公告)日：2012-12-11
申请号：US12769779
申请日：2010-04-29
申请人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/735
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/66659
摘要： A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
摘要翻译：横向双扩散金属氧化物半导体器件包括具有第一导电性的阱区，具有第一导电类型的第一载流子再分布区，其中第二阱区位于阱区之下，以及在第二阱区下面的高掺杂掩埋层。高掺杂掩埋层具有第一导电类型，并且其掺杂剂浓度小于阱区的掺杂浓度，并且小于第一载流子再分布区的掺杂浓度，并且掩埋层与第一阱区相连。此外，公开了可以使用外延生长的横向双重扩散金属氧化物半导体器件的形成方法。

54. 发明申请

US20120061758A1 SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US20120061758A1
公开(公告)日：2012-03-15
申请号：US12882899
申请日：2010-09-15
申请人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78 , H01L29/00 , H01L21/20
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译：这里介绍一种半导体器件和相关的制造工艺。该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。该器件还包括第二，第三，第四和第五半导体区域。第二半导体区域位于第一半导体区域的上方，具有第二导电型。第三半导体区域位于第二半导体区域的上方，具有第一导电型。第四半导体区域位于第三半导体区域的上方，具有第二导电型。第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。

55. 发明申请

US20120018804A1 Guard Ring Integrated LDMOS 有权
标题翻译：保护环集成LDMOS
公开(公告)号：US20120018804A1
公开(公告)日：2012-01-26
申请号：US12842660
申请日：2010-07-23
申请人： Vishnu K. Khemka , Stephen J. Cosentino , Tahir A. Khan , Adolfo C. Reyes , Ronghua Zhu
发明人： Vishnu K. Khemka , Stephen J. Cosentino , Tahir A. Khan , Adolfo C. Reyes , Ronghua Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1083 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/66681 , H01L29/7816 , H01L29/7817
摘要： An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).
摘要翻译：提供了一种LDMOSFET晶体管（100），其包括衬底（101），其中形成有漏极区（116）的外延漂移区（104），源区（112）为其中的第一阱区形成邻近源区（112）形成第一沟道区（14）的栅电极（120），以及接地衬底注入抑制保护结构，其包括与隔离欧姆接触的图案化掩埋层（102）阱区域（103）形成在衬底的预定上部区域中，以与第一阱区域（107）和漏极区域（116）间隔开，其中掩埋层（102）设置在第一阱区域（107），但不在漏极区域（116）的下方。

56. 发明申请

US20110309442A1 LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR HAVING A REDUCED SURFACE FIELD STRUCTURE AND METHOD THEREFOR 有权
标题翻译：具有减少表面的双向扩散金属氧化物半导体晶体管现场结构及其方法
公开(公告)号：US20110309442A1
公开(公告)日：2011-12-22
申请号：US12817805
申请日：2010-06-17
申请人： Bernhard H. Grote , Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
发明人： Bernhard H. Grote , Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7824
摘要： An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.
摘要翻译： LDMOS晶体管包括半导体材料的衬底，覆盖衬底的绝缘体层，覆盖绝缘体层的半导体层，RESURF区域和栅极。半导体层包括第一导电类型阱区，与第一导电类型阱区接触的第二导电类型源区，第二导电类型漏区。 RESURF区域包括至少一个第一导电类型的材料部分，以及电耦合到第一导电类型阱区的至少一个第一导电型材料部分的至少一部分。具有第二导电类型的半导体材料位于RESURF区域的下方。第二导电型半导体材料也位于RESURF区域的一部分上。栅极位于第一导电类型阱区域和RESURF区域之上。

57. 发明申请

US20110266614A1 LDMOS WITH ENHANCED SAFE OPERATING AREA (SOA) AND METHOD THEREFOR 有权
标题翻译：具有增强安全操作区（SOA）的LDMOS及其方法
公开(公告)号：US20110266614A1
公开(公告)日：2011-11-03
申请号：US12769779
申请日：2010-04-29
申请人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/66659
摘要： A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
摘要翻译：横向双扩散金属氧化物半导体器件包括具有第一导电性的阱区，具有第一导电类型的第一载流子再分布区，其中第二阱区位于阱区之下，以及在第二阱区下面的高掺杂掩埋层。高掺杂掩埋层具有第一导电类型，并且其掺杂剂浓度小于阱区的掺杂浓度，并且小于第一载流子再分布区的掺杂浓度，并且掩埋层与第一阱区相连。此外，公开了可以使用外延生长的横向双重扩散金属氧化物半导体器件的形成方法。

58. 发明申请

US20110241092A1 ELECTRONIC DEVICE WITH CAPCITIVELY COUPLED FLOATING BURIED LAYER 有权
标题翻译：具有高性能耦合浮动覆层的电子器件
公开(公告)号：US20110241092A1
公开(公告)日：2011-10-06
申请号：US12750166
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Ronghua Zhu , Weixiao Huang , Bernhard H. Grote
发明人： Vishnu K. Khemka , Tahir A. Khan , Ronghua Zhu , Weixiao Huang , Bernhard H. Grote
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译：使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。该改进对于LDMOS器件特别有用。

59. 发明申请

US20100230736A1 High Voltage Deep Trench Capacitor 有权
标题翻译：高压深沟槽电容器
公开(公告)号：US20100230736A1
公开(公告)日：2010-09-16
申请号：US12791996
申请日：2010-06-02
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

60. 发明申请

US20080265291A1 MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS 有权
标题翻译：包括具有替代P型和N型区域的源的MOSFET器件
公开(公告)号：US20080265291A1
公开(公告)日：2008-10-30
申请号：US11742363
申请日：2007-04-30
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/1087 , H01L29/456 , H01L29/7835
摘要： Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well. An area (510) comprising regions of alternating conductivities is then formed in the semiconductor well.
摘要翻译：提供了用于制造具有降低的双极效应的半导体器件的装置和方法。一种装置包括半导体本体（120），其包括位于半导体本体附近的表面和晶体管源（300），并且晶体管源包括交替导电区域（3110,3120）的区域（310）。另一种装置包括：半导体本体（120），其包括位于半导体本体中的第一导电性和晶体管源（500）。晶体管源包括包括第二导电性的多个区域（5120），其中所述区域和半导体主体形成第一和第二电导率的交替区域的区域（510）。一种方法包括在衬底（110）中注入包括第一导电性的半导体阱（120），并在半导体阱中注入包含第二导电性的多个掺杂区域（5120）。然后在半导体阱中形成包括交变电导率区域的区域（510）。

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