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    • 52. 发明申请
    • Method and system for applying a watermark
    • 应用水印的方法和系统
    • US20050129270A1
    • 2005-06-16
    • US10778995
    • 2004-02-13
    • Ravi Prakash
    • Ravi Prakash
    • G06K17/00G06T1/00G06K9/00G06K1/00B41B1/00
    • G06T1/0071G06K17/00
    • A system and method of imaging a document wherein a watermark is created and applied to the image. The watermark includes identifying information and may include information to determine whether the image has been altered since its creation. In a system where a single document (such as a check) is used to create multiple images (in the case of a check, an image of the front and back may be created in different manners, such as with different resolution or different levels of grey-scale). The use of a single watermark for multiple images of the same check can be used to determine that the multiple images are in fact of a single document and not of different documents, either though mistake or deception. A digitized image of the document is stored and a watermark associated with the document is generated and overlaid on the image to create a watermark on the image of the document for later use and processing.
    • 一种用于对其中创建水印并将其应用于图像的文档成像的系统和方法。 水印包括识别信息,并且可以包括用于确定图像自创建以来是否已被改变的信息。 在使用单个文档(例如支票)来创建多个图像的系统中(在检查的情况下,可以以不同的方式创建前后图像,例如具有不同分辨率或不同级别的 灰度)。 对于相同检查的多个图像使用单个水印可以用于确定多个图像实际上是单个文档,而不是不同的文档,尽管是错误或欺骗。 存储文档的数字化图像,并且生成与文档相关联的水印并将其覆盖在图像上以在文档的图像上创建水印以供稍后使用和处理。
    • 53. 发明授权
    • Clusterhead selection in wireless ad hoc networks
    • 无线自组织网络中的簇头选择
    • US06829222B2
    • 2004-12-07
    • US09841746
    • 2001-04-24
    • Alan Dewayne AmisRavi Prakash
    • Alan Dewayne AmisRavi Prakash
    • H04J1228
    • H04L29/12254H04L41/0893H04L45/04H04L45/46H04L61/2038H04W8/26H04W40/30H04W40/32H04W48/20H04W84/18
    • A system and method is disclosed wherein a plurality of nodes within an ad hoc wireless network are able to wirelessly communicate with each other. Each node includes a first data array for storing a node identifier used in selecting a clusterhead and a second data array for storing information relating to the node providing the node identifier for selecting the clusterhead to the node. Control logic of each node is configured according to a heuristic wherein the node initially determines a largest and smallest node identifier for each node. The node selects a clusterhead for the node responsive to the largest node identifier and the smallest node identifier using a set of predefined rules. The nodes within the area are then linked with the selected clusterhead.
    • 公开了一种系统和方法,其中自组织无线网络内的多个节点能够彼此无线通信。 每个节点包括用于存储用于选择簇头的节点标识符的第一数据阵列和用于存储与提供节点标识符的节点有关的信息的第二数据阵列,用于向节点选择簇头。 根据启发式配置每个节点的控制逻辑,其中节点最初确定每个节点的最大和最小节点标识符。 该节点使用一组预定义的规则来响应于最大节点标识符和最小节点标识符来选择节点的簇头。 然后区域内的节点与选定的集群头相连。
    • 54. 发明授权
    • Erase method for page mode multiple bits-per-cell flash EEPROM
    • 页面模式的擦除方式多个每位单元闪存EEPROM
    • US5675537A
    • 1997-10-07
    • US701288
    • 1996-08-22
    • Colin Stewart BillJonathan Shichang SuRavi Prakash Gutala
    • Colin Stewart BillJonathan Shichang SuRavi Prakash Gutala
    • G11C11/56G11C11/34
    • G11C11/5628G11C11/5621G11C11/5635G11C2211/5621
    • An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and an erase verify reference cell array for generating an upper erased state threshold voltage level. A pre-charge circuit (36a) is used to pre-charge all the array bit lines to a predetermined potential prior to a programming back operation. A reference generator circuit (134) is used for generating a reference output voltage corresponding to a lower erased state threshold voltage level. A switching circuit (P1, N1) is used to selectively disconnect a program current source of approximately 5 .mu.A from the selected certain ones of the columns of array bit lines containing the selected memory core cells which have been correctly programmed back. A sense logic circuit (26, 27) continuously compares a potential on one of the selected bit lines and the reference output voltage corresponding to the lower erase threshold voltage level. The sensing logic circuit generates a logic signal which is switched to a low logic level when the potential on the selected bit line falls below the bit line voltage corresponding to the lower erased state threshold voltage level. The switching circuit is responsive to the low logic level for disconnecting the programming current source so as to inhibit further programming back of the selected memory core cells.
    • 提供了一种改进的擦除结构,用于在多个比特单元闪存EEPROM存储器单元的阵列中执行擦除脉冲之后执行编程反向操作和并发验证操作。 存储器核心阵列(12)包括多个存储单元和用于产生上擦除状态阈值电压电平的擦除验证参考单元阵列。 预充电电路(36a)用于在编程回送操作之前将所有阵列位线预充电到预定电位。 参考发生器电路(134)用于产生对应于较低擦除状态阈值电压电平的参考输出电压。 开关电路(P1,N1)用于选择性地断开大约5μA的编程电流源与包含已经被正确编程回来的所选择的存储器核心单元的所选择的阵列位线列。 感测逻辑电路(26,27)连续地比较所选位线之一上的电位和对应于较低擦除阈值电压电平的参考输出电压。 当所选位线上的电位低于对应于较低擦除状态阈值电压电平的位线电压时,感测逻辑电路产生逻辑信号,该逻辑信号被切换到低逻辑电平。 开关电路响应于低逻辑电平以断开编程电流源,以便禁止所选存储器核心单元进一步编程。