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51. 发明申请

US20060195766A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060195766A1
公开(公告)日：2006-08-31
申请号：US11414826
申请日：2006-05-01
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C29/00
CPC分类号： H03M13/6566 , G06F11/1068 , H03M13/152 , H03M13/158
摘要： An ECC circuit (103) is located between I/O terminals (1040-1047) and page buffers (1020-1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010-1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010-1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=528×8 to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).
摘要翻译： ECC电路（103）位于I / O端子（104）和页面缓冲器（102）之间， SUB> 7 ）。 ECC电路（103）包括编码器，其被配置为产生用于纠错的校验位（ECC），并将校验位附加到要写入多个存储单元区域的数据（101 < SUB＆gt; 7＆gt;）和解码器，被配置为使用所生成的校验位（ECC）来纠错从存储单元区域读出的数据（101＆lt; ）。 ECC电路（103）将一组40个校验位（ECC）分配给4224 = 528×8的信息位长度，以通过并行处理8位数据执行编码和解码，其中将528位的数据定义为从一个存储单元区域（101j）写入和读出。

52. 发明授权

US07076722B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07076722B2
公开(公告)日：2006-07-11
申请号：US10292397
申请日：2002-11-12
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C29/00
CPC分类号： H03M13/6566 , G06F11/1068 , H03M13/152 , H03M13/158
摘要： An ECC circuit (103) is located between I/O terminals (1040–1047) and page buffers (1020–1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010–1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010–1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=(528×8) bits to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).
摘要翻译： ECC电路（103）位于I / O端子之间（104 <0> -104＆lt; 7＆gt;）和页缓冲器（102＆lt; 0＆gt; -102＆ SUB> 7 ）。 ECC电路（103）包括编码器，其被配置为产生用于纠错的校验位（ECC），并将校验位附加到要写入多个存储单元区域的数据（101 < SUB＆gt; 7＆gt;）和解码器，被配置为使用所生成的校验位（ECC）来对从存储器单元区域读出的数据进行错误校正（101＆lt; 0＆gt; ）。 ECC电路（103）将一组40个校验位（ECC）分配给信息位长度为4224 =（528×8）位，以通过并行处理8位数据执行编码和解码，其中将528位的数据定义为单元被写入并从一个存储单元区域读出（101 ）。

53. 发明申请

US20060126392A1 High-speed verifiable semiconductor memory device 有权
公开(公告)号：US20060126392A1
公开(公告)日：2006-06-15
申请号：US11297467
申请日：2005-12-09
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/3436 , G11C16/3404
摘要： A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.

54. 发明申请

US20060120162A1 Method of writing data to a semiconductor memory device 有权
公开(公告)号：US20060120162A1
公开(公告)日：2006-06-08
申请号：US11270499
申请日：2005-11-10
申请人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
发明人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/28 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648 , G11C2216/14
摘要： A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

55. 发明授权

US07016226B2 Semiconductor memory device for storing multivalued data 有权
公开(公告)号：US07016226B2
公开(公告)日：2006-03-21
申请号：US10764828
申请日：2004-01-26
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

56. 发明授权

US06962552B2 Vehicle shift control device and control method therefor 失效
标题翻译：车辆换档控制装置及其控制方法
公开(公告)号：US06962552B2
公开(公告)日：2005-11-08
申请号：US10207976
申请日：2002-07-31
申请人： Naoyuki Sakamoto , Kazuyuki Watanabe , Toshimitsu Sato , Atsushi Ayabe , Hiromichi Kimura , Hideaki Ogasawara , Noboru Shibata , Mitsuhiro Nakamura
发明人： Naoyuki Sakamoto , Kazuyuki Watanabe , Toshimitsu Sato , Atsushi Ayabe , Hiromichi Kimura , Hideaki Ogasawara , Noboru Shibata , Mitsuhiro Nakamura
IPC分类号： F16H3/66 , F16H59/38 , F16H61/00 , F16H61/06 , F16H61/686 , F16H61/04
CPC分类号： F16H61/061 , F16H3/66 , F16H61/686 , F16H2059/385 , F16H2059/425 , F16H2061/0087 , F16H2200/0047 , F16H2306/44 , F16H2306/52 , Y10T477/69387
摘要： A duty ratio for controlling an engagement force of a friction engagement device on the side of upshift engagement is corrected by an amount corresponding to an intermediate correction control value in the course of the shift. In addition, on a prerequisite condition that learning correction of a constant standby pressure control value at the start of the shift is converged, learning correction is performed for the intermediate correction control value according to a gradient of a turbine speed. Thus, a shift shock is prevented from occurring due to abrupt engagement of the friction engagement device and the like at the completion of the shift.
摘要翻译：用于控制摩擦接合装置在升档接合侧的接合力的占空比通过与换档过程中的中间校正控制值对应的量来校正。此外，在变速开始时的恒定待机压力控制值的学习校正被收敛的先决条件下，根据涡轮转速的梯度对中间校正控制值进行学习校正。因此，在变速结束时，由于摩擦接合装置等的突然接合，防止发生换挡冲击。

57. 发明授权

US06944055B2 Semiconductor memory device and storage method thereof 有权
标题翻译：半导体存储器件及其存储方法
公开(公告)号：US06944055B2
公开(公告)日：2005-09-13
申请号：US10762827
申请日：2004-01-21
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/02 , G11C7/00 , G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/5621 , G11C2211/5642
摘要： For a verify operation using potential Vbi′, the data of a memory cell is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi′. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.
摘要翻译：对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元的数据，并将存储单元的状态存储在锁存电路中。然后，通过使用电位Vbi'进行验证/读取操作。如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。因此，只需要两个锁存电路来存储n位数据，包括一个用于存储要写入的数据的数据，一个用于在小区的状态高于Ai + 1时预先读取，并且存储初步阅读。

58. 发明授权

US06903981B2 Non-volatile semiconductor memory device, method for sub-block erase and electric device with the same 失效
标题翻译：非易失性半导体存储器件，子块擦除方法和电子器件相同
公开(公告)号：US06903981B2
公开(公告)日：2005-06-07
申请号：US10678179
申请日：2003-10-06
申请人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
发明人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34
CPC分类号： G11C16/3445 , G11C16/04 , G11C16/16 , G11C16/3436 , G11C16/3459 , G11C29/50004
摘要： After execution of sub-block erase (S2) for partly erasing a memory cell block, sub-block erase verify read is executed (S4). As a result of the sub-block erase verify read, if the sub-block erase is completed, then terminate the sub-block erase (S5). If otherwise the sub-block erase is not completed yet, then perform over-program verify read (S6) to thereby determine whether the cause of an event that a sub-block erase-verify result becomes “Fail” due to the deficiency of erase or the presence of an over-programmed cell or cells. If the result of such over-program verify read is “Pass,” then repeat execution of the sub-block erase verify read (S2). When the over-program verify read (S6) is “Fail,” output a Fail result and then complete the operation (S8).
摘要翻译：在执行用于部分擦除存储单元块的子块擦除（S 2）之后，执行子块擦除验证读取（S 4）。作为子块擦除验证读取的结果，如果子块擦除完成，则终止子块擦除（S 5）。否则子块擦除尚未完成，则执行过程编程验证读取（S 6），从而确定子块擦除验证结果由于不足而导致的“失败”事件的原因擦除或过度编程的细胞或细胞的存在。如果这种过程编程验证读取的结果为“通过”，则重复执行子块擦除验证读取（S 2）。当过程程序验证读取（S 6）为“失败”时，输出失败结果，然后完成操作（S 8）。

59. 发明申请

US20050047217A1 Semiconductor memory device for storing multivalued data 有权
标题翻译：用于存储多值数据的半导体存储器件
公开(公告)号：US20050047217A1
公开(公告)日：2005-03-03
申请号：US10689868
申请日：2003-10-20
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/10 , G11C11/56 , G11C16/04 , G11C16/12 , G11C5/00
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C2211/5642 , G11C2211/5648
摘要： In the operation of writing the second page, the control circuit precharges the bit line in verifying data “2” in the memory cell when the DDC has data “1” in it after the data cache is set and does not precharge the bit line when the DDC has data “0” in it. As a result, when data “2” has been written into the memory cell, the bit line is at the intermediate potential, which raises the threshold voltage of the memory cell a little.
摘要翻译：在写入第二页的操作中，当DDC在数据高速缓冲存储器设置之后具有数据“1”时，控制电路对存储单元中的数据“2”中的位线进行预充电，并且当位线不预充电时， DDC中有数据“0”。结果，当数据“2”已写入存储单元时，位线处于中间电位，这使存储单元的阈值电压稍微升高。

60. 发明授权

US06843756B2 Downshift control apparatus of vehicular automatic transmission, and control method thereof 有权
标题翻译：车辆自动变速器的降档控制装置及其控制方法
公开(公告)号：US06843756B2
公开(公告)日：2005-01-18
申请号：US10639621
申请日：2003-08-13
申请人： Toshimitsu Sato , Hisanori Nomoto , Naoyuki Sakamoto , Toshio Sugimura , Hiromichi Kimura , Yoshiharu Harada , Noboru Shibata
发明人： Toshimitsu Sato , Hisanori Nomoto , Naoyuki Sakamoto , Toshio Sugimura , Hiromichi Kimura , Yoshiharu Harada , Noboru Shibata
IPC分类号： B60W10/04 , B60W10/06 , B60W10/10 , B60W10/11 , F16H3/66 , F16H59/24 , F16H59/42 , F16H61/04 , F16H61/06 , F16H61/08 , F16H63/50
CPC分类号： F16H61/061 , F16H3/64 , F16H3/66 , F16H63/502 , Y10T477/675 , Y10T477/679 , Y10T477/69373 , Y10T477/693754 , Y10T477/693762
摘要： In a vehicle in which a moderate throttle opening degree control of maintaining a degree of throttle opening that is less than a degree of throttle opening that corresponds to an accelerator operation is performed for a predetermined period following a beginning of the accelerator operation, if it is determined that a clutch-to-clutch downshift judgment has been made, the reduction of the engaging pressure of a disengage-side friction engagement device is restrained until it is determined that the moderate throttle opening degree control has ended. Therefore, even if the turbine torque is returned to a normal value at the end of the moderate throttle opening degree control, insufficient engaging torque is avoided, and the takeover of engaging torque for the clutch-to-clutch downshift is smoothly performed while the turbine torque is stable. Hence, occurrence of a shock related to the end of the moderate throttle opening degree control is suitably prevented.
摘要翻译：在加速器操作开始之后的预定时间内进行保持节气门开度小于对应于加速器操作的节气门开度的中等节气门开度控制的车辆，如果是确定已经进行离合器离合器降档判定，从而抑制了解除侧摩擦接合装置的接合压力的降低，直到确定适度的节气门开度控制已经结束为止。因此，即使在适度的节气门开度控制结束时涡轮转矩恢复到正常值，也避免了不充分的接合扭矩，并且平稳地执行离合器离合器降档的接合扭矩的接收，同时涡轮扭矩稳定。因此，适当地防止与适度的节气门开度控制的结束相关的冲击的发生。

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