专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US5271006A Frame aligner and method and system for control thereof 失效
标题翻译：框架对准器及其控制方法和系统
公开(公告)号：US5271006A
公开(公告)日：1993-12-14
申请号：US663956
申请日：1991-03-19
申请人： Yoshihiro Ashi , Tadayuki Kanno , Masahiro Takatori , Hiromi Ueda
发明人： Yoshihiro Ashi , Tadayuki Kanno , Masahiro Takatori , Hiromi Ueda
IPC分类号： H04J3/06 , H04J3/22
CPC分类号： H04J3/0629
摘要： A frame aligner and a method and system for control thereof, in which the frame alignment is executed while assuring TSSI (Time Slot Sequence Integrity). In a system for transmitting a plurality of low-speed signals having a frame structure in a high-speed frame, a plurality of candidates for a write start phase for a frame aligner memory are set, and by accessing a common phase memory storing a write start phase shared by low-speed signals requiring phase matching therebetween of all the low-speed signals stored in the high-speed frame, a write start phase is selected from among the candidates for the write start phase for the frame aligner memory.
摘要翻译： PCT No.PCT / JP90 / 00925 Sec。 371日期1991年3月19日 102（e）1991年3月19日PCT PCT 1990年7月18日PCT公布。公开号WO91 / 01601 日期1991年2月7日。一种帧对准器及其控制方法和系统，其中在确保TSSI（时隙序列完整性）的同时执行帧对准。在用于发送具有高速帧中的帧结构的多个低速信号的系统中，设置用于帧对准器存储器的写入开始阶段的多个候选，并且通过访问存储写入的公共相位存储器低速信号共享的起始相位需要存储在高速帧中的所有低速信号之间的相位匹配，从用于帧对准器存储器的写入开始相位的候选中选择写入开始相位。

52. 发明授权

US5197063A Circuit switching method and apparatus for time division network with various transmission speeds 失效
标题翻译：具有各种传输速度的时分网络的电路交换方法和装置
公开(公告)号：US5197063A
公开(公告)日：1993-03-23
申请号：US641928
申请日：1991-01-16
申请人： Yukio Nakano , Tadayuki Kanno , Masahiro Takatori , Hiromi Ueda
发明人： Yukio Nakano , Tadayuki Kanno , Masahiro Takatori , Hiromi Ueda
IPC分类号： H04J3/22 , H04J3/00 , H04J3/16 , H04Q11/04
CPC分类号： H04Q11/04 , H04J3/1611
摘要： A circuit switching apparatus and method for time division network with various transmission speeds for time-division multiplexing a plurality of circuits including signals at different transmission speeds, transmitting the same onto an input highway, repeatedly recording the transmitted signals in a data memory in a predetermined order, reading respective recorded signals in a predetermined order onto an output highway. An access unit for reading signals from the data memory has an address control memory for storing circuit switching information, a circuit speed control memory for storing transmission speed information for the respective circuits and an address generating section for generating an address for accessing the data memory on the basis of the circuit switching information and the circuit transmission speed information from those memories.
摘要翻译：一种用于具有各种传输速度的时分网络的电路交换装置和方法，用于对包括不同传输速度的信号的多个电路进行时分复用，将其发送到输入公路上，以预定的方式将数据存储器重复地记录发送的信号以预定顺序将各个记录信号读出到输出高速公路上。用于从数据存储器读取信号的访问单元具有用于存储电路切换信息的地址控制存储器，用于存储各个电路的传输速度信息的电路速度控制存储器和用于生成访问数据存储器的地址的地址生成部分电路切换信息的基础和来自这些存储器的电路传输速度信息。

53. 发明授权

US08483063B2 Mobile communication system and communication method 有权
标题翻译：移动通信系统及通信方式
公开(公告)号：US08483063B2
公开(公告)日：2013-07-09
申请号：US12987665
申请日：2011-01-10
申请人： Masashi Yano , Masahiro Takatori , Naruhito Nakahara , Nodoka Mimura
发明人： Masashi Yano , Masahiro Takatori , Naruhito Nakahara , Nodoka Mimura
IPC分类号： H04J3/16
CPC分类号： H04L47/14 , H04L1/1635 , H04L1/1854 , H04L12/66 , H04L43/0894 , H04L47/225 , H04L47/283 , H04L47/323 , H04L2001/0097 , H04W28/14 , H04W88/04 , H04W88/08 , H04W88/16
摘要： Disclosed is a mobile communication system preventing the transmission of acknowledgements at a burst leading to a decrease in throughput caused by detecting the retransmission and the congestion of packets at the protocol of a transport layer. In a mobile communication system including a mobile terminal and gateway equipment for relaying a packet between a communication partner and the mobile terminal, if the gateway equipment receives the acknowledgement from the mobile terminal, the gateway equipment waits the transmission of the received acknowledgement to the communication partner until the estimated transmission time passes from the time at which the gateway equipment receives the previous acknowledgement from the mobile terminal.
摘要翻译：公开了一种移动通信系统，其防止在突发情况下发送确认，从而导致通过检测传输层的协议的分组的重传和拥塞而导致的吞吐量的降低。在包括用于在通信伙伴和移动终端之间中继分组的移动终端和网关设备的移动通信系统中，如果网关设备从移动终端接收到确认，则网关设备等待所接收到的确认传送到通信伙伴，直到估计传输时间从网关设备从移动终端接收到先前确认的时间过去。

54. 发明申请

US20120177004A1 Network System and Network Apparatus 有权
标题翻译：网络系统和网络设备
公开(公告)号：US20120177004A1
公开(公告)日：2012-07-12
申请号：US13327402
申请日：2011-12-15
申请人： Masashi YANO , Nodoka MIMURA , Masahiro TAKATORI , Naruhito NAKAHARA
发明人： Masashi YANO , Nodoka MIMURA , Masahiro TAKATORI , Naruhito NAKAHARA
IPC分类号： H04W36/08
CPC分类号： H04L45/50 , H04L45/507 , H04L47/824 , H04L47/825 , H04W36/00 , H04W76/10 , H04W88/02 , H04W88/08 , H04W88/16
摘要： After a first base station connects to a first mobile terminal, a first GW (gateway) receives a request for connection between the first mobile terminal and a second GW and identifiers of the second GW and the first mobile terminal and transmits identifiers of the first mobile terminal and the first GW to the second GW. The second GW transmits an MPLS allocation flag to the first GW. The first GW transmits an MPLS allocation signal including an identifier of the first mobile terminal to the second GW via a second NW (network) apparatus. The first base station receives an identifier of the first GW and the MPLS allocation flag from the first GW via a management server and transmits the MPLS allocation signal including the identifier of the first mobile terminal to the first GW via a first NW apparatus.
摘要翻译：在第一基站连接到第一移动终端之后，第一GW（网关）接收第一移动终端和第二GW之间的连接请求以及第二GW和第一移动终端的标识符，并且发送第一移动终端终端和第一GW到第二GW。第二GW向第一GW发送MPLS分配标志。第一GW经由第二NW（网络）装置向第二GW发送包括第一移动终端的标识符的MPLS分配信号。第一基站经由管理服务器从第一GW接收到第一GW的标识符和MPLS分配标志，经由第一NW设备向第一GW发送包含第一移动终端的标识符的MPLS分配信号。

55. 发明申请

US20100184432A1 MOBILE COMMUNICATION SYSTEM FOR LOW POWER CONSUMPTION, CALL CONTROL SERVER AND ACCESS GATEWAY 失效
标题翻译：用于低功耗的移动通信系统，呼叫控制服务器和访问网关
公开(公告)号：US20100184432A1
公开(公告)日：2010-07-22
申请号：US12690455
申请日：2010-01-20
申请人： Masashi YANO , Hitomi NAKAMURA , Masahiro TAKATORI , Takehiro MORISHIGE , Yoshihiro SHIMIZU
发明人： Masashi YANO , Hitomi NAKAMURA , Masahiro TAKATORI , Takehiro MORISHIGE , Yoshihiro SHIMIZU
IPC分类号： H04W4/00 , H04W36/00 , G08C17/00
CPC分类号： H04W36/12 , H04W28/08 , H04W60/02 , Y02D70/1224 , Y02D70/1262 , Y02D70/146
摘要： It is provided a mobile communication system comprising base stations, call control servers and access gateways. The call control servers cause a mobile terminal accommodated in one of the control server to transmit the location registration request so that the mobile terminal accommodates in another control server according to a processing amount of control signals. The base station selects a second call control server into which the one of the mobile terminals is to be newly accommodated. The one of the call control server switches to a power-saving state after the mobile terminal is accommodated into the another call control server.
摘要翻译：提供了一种包括基站，呼叫控制服务器和接入网关的移动通信系统。呼叫控制服务器使得容纳在一个控制服务器中的移动终端发送位置登记请求，使得移动终端根据控制信号的处理量容纳在另一个控制服务器中。基站选择要容纳新移动终端中的一个的第二呼叫控制服务器。呼叫控制服务器中的一个在移动终端被容纳到另一个呼叫控制服务器之后切换到省电状态。

56. 发明申请

US20100182854A1 OPERATION GUARANTEE SYSTEM 有权
标题翻译：操作保证系统
公开(公告)号：US20100182854A1
公开(公告)日：2010-07-22
申请号：US12668336
申请日：2008-06-27
申请人： Masahiro Takatori
发明人： Masahiro Takatori
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.
摘要翻译：操作保证系统包括解码器电路，比较电路，CPU电路，频率调整电路和DQ调整电路。比较电路将从解码器电路输入的测试数据信号与从外部输入的期望值数据信号进行比较，并且检测解码器电路中是否存在输出错误。 CPU电路控制频率调整电路和DQ调整电路，以改变输入到外部存储器的时钟信号的频率和数据信号的延迟量。此外，CPU电路在各种条件下获取比较电路的检测结果。然后，CPU电路基于各种条件与输出错误的存在或不存在之间的关系来确定输入到外部存储器的时钟信号的适当频率。

57. 发明申请

US20080205016A1 Module Board 有权
标题翻译：模块板
公开(公告)号：US20080205016A1
公开(公告)日：2008-08-28
申请号：US11908726
申请日：2006-03-15
申请人： Masahiro Takatori , Yukihiro Ishimaru
发明人： Masahiro Takatori , Yukihiro Ishimaru
IPC分类号： H05K1/14
CPC分类号： H01L25/0652 , H01L23/5385 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0268 , H05K1/112 , H05K1/117 , H05K1/185 , H05K3/4611 , H05K2201/0919 , H05K2201/09845 , H01L2924/00 , H01L2924/00012
摘要： A module board has a configuration in which a first circuit board, a first composite sheet, a second circuit board, a second composite sheet, and a third circuit board are laminated in this order. Inspection terminals are arranged in a matrix shape in a predetermined region on an upper surface of the third circuit board. Electronic components are mounted on the first and second circuit boards. The inspection terminals are electrically connected to the electronic components mounted on the first and second circuit boards through vias and wiring patterns.
摘要翻译：模块板具有以下顺序构造第一电路板，第一复合片，第二电路板，第二复合片和第三电路板。检查端子在第三电路板的上表面上的预定区域中以矩阵形状布置。电子部件安装在第一和第二电路板上。检查端子通过通孔和布线图形电连接到安装在第一和第二电路板上的电子部件。

58. 发明授权

US07304997B2 Reception system for replacing transport packets 有权
标题翻译：接收系统，用于替换传输数据包
公开(公告)号：US07304997B2
公开(公告)日：2007-12-04
申请号：US11157881
申请日：2005-06-21
申请人： Masahiro Takatori , Hidekazu Suzuki
发明人： Masahiro Takatori , Hidekazu Suzuki
IPC分类号： H04L12/28
CPC分类号： H04N7/163 , H04N5/4401 , H04N5/44543 , H04N21/4334 , H04N21/434 , H04N21/4344 , H04N21/4345
摘要： A reception system has a receiving section which receives a transport stream transmitted from a transmission system that produces and transmits the transport stream, the transport stream being produced by multiplexing compression coded contents of a program, and electronic program guide information including program specific information having at least an NIT, a PAT, and a PMT, and service information having at least an SDT and an EIT; a PID designating section which can designate a PID of a packet other than an NIT packet in the electronic program guide information, as a PID of a replace packet (hereinafter, referred to as replace PID); a replace PID storing device which stores the replace PID; an SIT producing section which produces an SIT packet from the service information in the received transport stream; and a packet extracting and replacing section which can replace a replace packet indicated by said replace PID storing device, and the NIT packet with the SIT packet.
摘要翻译：接收系统具有：接收部，其接收从传输系统发送的传输流，所述传输流生成并发送传输流，所述传输流是通过复用节目的压缩编码内容产生的，以及包括节目特定信息的电子节目指南信息，至少NIT，PAT和PMT，以及具有至少SDT和EIT的服务信息; PID指定部，其可以将电子节目指南信息中的NIT分组以外的分组的PID指定为替换分组的PID（以下称为替换PID）; 存储替换PID的替换PID存储装置; SIT产生部分，根据所接收的传输流中的服务信息产生SIT分组; 以及可以替换由所述替换PID存储装置指示的替换分组的分组提取和替换部分，以及具有SIT分组的NIT分组。

59. 发明申请

US20060212780A1 Method for encoding/decoding error correcting code, transmitting apparatus and network 失效
标题翻译：纠错码，发送装置和网络的编码/解码方法
公开(公告)号：US20060212780A1
公开(公告)日：2006-09-21
申请号：US11344579
申请日：2006-01-30
申请人： Masaki Ohira , Masahiro Takatori , Takashi Mori
发明人： Masaki Ohira , Masahiro Takatori , Takashi Mori
IPC分类号： H03M13/00
CPC分类号： H04L1/0083
摘要： A client signal having a constant bit rate is segmented every a bytes to create code information blocks. The bit rate of the client signal is increased such that the client signal has the code information block and an empty area comprised of b bytes, and the ratio c/a is equal to or higher than 110% to create a code block 3 comprised of c bytes. The code information block in the code block is encoded such that an error correcting code is included therein to have an encoding gain of 6 dB or higher for a bit error ratio of 10−12. Associated check bits are placed in the empty area to eventually generate a super FEC signal.
摘要翻译：具有恒定比特率的客户端信号每隔一个字节分段以产生代码信息块。客户端信号的比特率增加，使得客户端信号具有代码信息块和由b字节组成的空白区域，并且比率c / a等于或高于110％以创建由 c字节。代码块中的代码信息块被编码为使得纠错码被包括在其中以使得对于误差比为10 -12的编码增益为6dB或更高。关联的校验位被放置在空区域中以最终生成超FEC信号。

60. 发明授权

US07024616B2 Method for encoding/decoding error correcting code, transmitting apparatus and network 失效
公开(公告)号：US07024616B2
公开(公告)日：2006-04-04
申请号：US09771733
申请日：2001-01-29
申请人： Masaki Ohira , Masahiro Takatori , Takashi Mori
发明人： Masaki Ohira , Masahiro Takatori , Takashi Mori
IPC分类号： H03M13/03
CPC分类号： H04L1/0083
摘要： A client signal having a constant bit rate is segmented every a bytes to create code information blocks. The bit rate of the client signal is increased such that the client signal has the code information block and an empty area comprised of b bytes, and the ratio c/a is equal to or higher than 110% to create a code block 3 comprised of c bytes. The code information block in the code block is encoded such that an error correcting code is included therein to have an encoding gain of 6 dB or higher for a bit error ratio of 10−12. Associated check bits are placed in the empty area to eventually generate a super FEC signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式