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51. 发明授权

US5909626A SOI substrate and fabrication process therefor 失效
标题翻译： SOI衬底及其制造工艺
公开(公告)号：US5909626A
公开(公告)日：1999-06-01
申请号：US826046
申请日：1997-03-28
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S438/977
摘要： After partially burying an insulation layer in a first single-crystalline silicon substrate, and flattening, the first single-crystalline silicon substrate and a second single-crystalline substrate are formed with a low impurity concentration epitaxial layer. By grinding and polishing the first single crystalline silicon substrate, an ultra thin film SOI layer having thickness of about 0.1 .mu.m is formed. On the ultra thin film SOI layer, an insulation layer 8 for isolation is formed. Thus, an SOI substrate for integrating the power element and a control circuit element including the ultra thin film SOI layer in one chip can be provided.
摘要翻译：在将第一单晶硅衬底中的绝缘层部分地埋入并平坦化之后，第一单晶硅衬底和第二单晶衬底形成有低杂质浓度的外延层。通过研磨和研磨第一单晶硅衬底，形成厚度为约0.1μm的超薄膜SOI层。在超薄膜SOI层上形成用于隔离的绝缘层8。因此，可以提供用于将功率元件和包括超薄膜SOI层的控制电路元件集成在一个芯片中的SOI衬底。

52. 发明授权

US5736779A Semiconductor device with Zener diode for gate protection, and method for fabricating the same 失效
标题翻译：具有用于栅极保护的齐纳二极管的半导体器件及其制造方法
公开(公告)号：US5736779A
公开(公告)日：1998-04-07
申请号：US681960
申请日：1996-07-30
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/76 , H01L27/02 , H01L27/04 , H01L27/06 , H01L29/78 , H01L29/866 , H01L23/62
CPC分类号： H01L29/7808 , H01L27/0255 , H01L27/0688 , H01L29/0638 , H01L29/7811 , H01L29/866 , H01L2924/0002
摘要： A semiconductor device has a Zener diode disposed between a gate and a source of a MOS type semiconductor device. The Zener diode is structured as N.sup.+ /P/P.sup.+ /P/N.sup.+. The P.sup.+ region functions as a channel stopper, and suppresses the occurrence of leakage current caused by an inversion of a surface of the low concentration P region. The adjustment of the width of the P.sup.+ region enables the controlling of a Zener voltage. The Zener diode protects the gate, and the arrangement enables the prevention of the occurrence of leakage current between the gate and the source.
摘要翻译：半导体器件具有设置在MOS型半导体器件的栅极和源极之间的齐纳二极管。齐纳二极管的结构为N + / P / P + / P / N +。 P +区域用作沟道阻挡层，并且抑制由低浓度P区域的表面的反转引起的漏电流的发生。调整P +区域的宽度可以控制齐纳电压。齐纳二极管保护栅极，并且该布置能够防止栅极和源极之间的漏电流的发生。

53. 发明授权

US5573972A Method for manufacturing a silicon bonded wafer 失效
标题翻译：硅键合晶片的制造方法
公开(公告)号：US5573972A
公开(公告)日：1996-11-12
申请号：US506980
申请日：1995-07-28
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012
摘要： A method for manufacturing a silicon bonded wafer includes the steps of preparing a first substrate of a lightly doped N-silicon having a plurality of V-grooves, preparing a second substrate of a heavily doped N-silicon having a first portion covered by an insulating film and a second portion having a top surface flush with the surface of the insulating film, bonding the first and the second substrates such that the V-grooves are located on the insulating film of the first portion of the second substrate, and grinding the first substrate at the back surface to provide a bonded wafer having a main surface exposing therein the bottom of the grooves. The grooves separate the bonded wafer into a power element forming region and a plurality of control circuit forming regions. The inverted V-grooves reduces less amount of areas for forming the control elements.
摘要翻译：一种制造硅键合晶片的方法包括以下步骤：制备具有多个V形槽的轻掺杂N型硅的第一衬底，制备重掺杂N-硅的第二衬底，其具有由绝缘体膜和具有与绝缘膜的表面齐平的顶表面的第二部分，将第一和第二基板接合，使得V形槽位于第二基板的第一部分的绝缘膜上，并且将第一衬底，以提供具有在其中暴露槽的底部的主表面的接合晶片。沟槽将接合晶片分离成功率元件形成区域和多个控制电路形成区域。倒V形凹槽减少了用于形成控制元件的区域的较少量。

54. 发明授权

US08222690B2 Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof 失效
标题翻译：具有分离的基极区域的垂直功率MOSFET半导体器件及其制造方法
公开(公告)号：US08222690B2
公开(公告)日：2012-07-17
申请号：US12923859
申请日：2010-10-12
申请人： Kinya Ohtani , Kenya Kobayashi
发明人： Kinya Ohtani , Kenya Kobayashi
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095
摘要： A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions.
摘要翻译：半导体装置包括形成在第一导电类型的半导体衬底上的掺杂半导体层和形成在半导体层中的第一和第二栅极沟槽，第二栅极沟槽在第一方向上与第一栅极沟槽分离。掺杂半导体层包括在第一和第二栅极沟槽之间形成的第二导电型的低浓度基极区域，第一导电类型的第一源极区域，第一导电类型的第二源极区域，第一高浓度基极区域的第二导电类型的第二高浓度碱基区域和形成为使得第一和第二高浓度碱基区域被低浓度碱基区域分离的第二高浓度碱性区域，并且第二高浓度碱性区域不低于第一和第二源区。

55. 发明授权

US07666744B2 Method of manufacturing a semiconductor device having a trench surrounding plural unit cells 有权
标题翻译：制造具有围绕多个单电池的沟槽的半导体器件的方法
公开(公告)号：US07666744B2
公开(公告)日：2010-02-23
申请号：US12165991
申请日：2008-07-01
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/8236
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and separated from the first source region, and a second base region formed in the first base region and disposed between the first and second source regions. The semiconductor device further comprises a trench gate formed in a vicinity of each of the plurality of unit cells. The second base region of an unit cell is separated from the second base region of an adjacent unit cell, and the first or second source region of an unit cell is separated from the first or second source region of an adjacent unit cell.
摘要翻译：半导体器件包括多个单元电池，每个单元电池包括垂直金属氧化物半导体场效应晶体管（MOSFET）。单位电池包括形成在第一基极区域中的第一源极区域，形成在第一基极区域中并与第一源极区域分离的第二源极区域和形成在第一基极区域中并且设置在第一和第二基极区域之间的第二基极区域第二源区。半导体器件还包括形成在多个单元电池中的每一个附近的沟槽栅极。单位单元的第二基区与相邻单元的第二基区分离，并且单位单元的第一或第二源区与相邻单元的第一或第二源区分离。

56. 发明申请

US20090072300A1 Semiconductor device having trench gate structure 失效
标题翻译：具有沟槽栅结构的半导体器件
公开(公告)号：US20090072300A1
公开(公告)日：2009-03-19
申请号：US12232074
申请日：2008-09-10
申请人： Hideo Yamamoto , Kenya Kobayashi , Atsushi Kaneko
发明人： Hideo Yamamoto , Kenya Kobayashi , Atsushi Kaneko
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L27/0727 , H01L29/0696 , H01L29/1095 , H01L29/7808
摘要： The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFET 100 comprises a plurality of gate trenches 7 which is arranged in stripes, an array which is sandwiched with the plurality of gate trenches 7 and includes N+ source regions 4N+ and P+ base contact regions 5P+, and a diode region (anode region 6P+) which is formed so as to contact with two gate trenches 7. The N+ source regions 4N+ and the base contact regions 5P+ are alternately arranged along a longitudinal direction of the gate trench 7. Size of the diode region (anode region 6P+) corresponds to at least one of the N+ source regions 4N+ and two of the P+ base contact regions 5P+.
摘要翻译：本发明提供了一种具有条纹沟槽栅极结构的垂直MOSFET，其可以在不增加Ron的情况下确保雪崩电阻。垂直MOSFET100包括多个栅极沟槽7，栅极沟槽7被布置成阵列，该阵列夹在多个栅极沟槽7之间并包括N +源极区域4N +和P +基极接触区域5P +，二极管区域（阳极区域6P + ）形成为与两个栅极沟槽7接触.N +源极区域4N +和基极接触区域5P +沿着栅极沟槽7的纵向方向交替排列。二极管区域（阳极区域6P +）的尺寸对应于 N +源极区域4N +和P +基极接触区域5P + +中的至少一个。

57. 发明授权

US06872631B2 Method of forming a trench isolation 失效
标题翻译：形成沟槽隔离的方法
公开(公告)号：US06872631B2
公开(公告)日：2005-03-29
申请号：US10607064
申请日：2003-06-27
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/76283
摘要： A method of forming a trench isolation in a substrate includes the steps of forming a trench groove in a substrate, forming a first electrically insulating layer which fills the trench groove and extends over an upper surface of the substrate, where the first electrically insulating layer has a first surface migration, and an upper surface of the first electrically insulating layer has a first hollow positioned over the trench groove, and forming a second electrically insulating layer over the first electrically insulating layer. The second electrically insulating layer fills the first hollow and an upper surface of the second electrically insulating layer has a second hollow positioned over the trench groove. The second electrically insulating layer has a second surface migration smaller than the first surface migration.
摘要翻译：在衬底中形成沟槽隔离的方法包括以下步骤：在衬底中形成沟槽，形成填充沟槽并在衬底的上表面上延伸的第一电绝缘层，其中第一电绝缘层具有所述第一电绝缘层的第一表面迁移和上表面具有位于所述沟槽上的第一中空孔，并且在所述第一电绝缘层上形成第二电绝缘层。第二电绝缘层填充第一中空部分，并且第二电绝缘层的上表面具有位于沟槽上方的第二中空部。第二电绝缘层具有小于第一表面迁移的第二表面迁移。

58. 发明授权

US06838356B2 Method of forming a trench isolation 失效
标题翻译：形成沟槽隔离的方法
公开(公告)号：US06838356B2
公开(公告)日：2005-01-04
申请号：US09956142
申请日：2001-09-20
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/76283
摘要： The present invention provides a method of forming a trench isolation in a substrate, which comprises the steps of: forming a trench groove in a substrate; forming a first electrically insulating layer which fills the trench groove and extends over an upper surface of the substrate, wherein the first electrically insulating layer has a first surface migration, and an upper surface of the first electrically insulating layer has a first hollow positioned over the trench groove; and forming a second electrically insulating layer over the first electrically insulating layer, wherein the second electrically insulating layer fills the first hollow, and an upper surface of the second electrically insulating layer has a second hollow positioned over the trench groove, and the second electrically insulating layer has a second surface migration smaller than the first surface migration.
摘要翻译：本发明提供一种在衬底中形成沟槽隔离的方法，其包括以下步骤：在衬底中形成沟槽; 形成第一电绝缘层，其填充所述沟槽并在所述衬底的上表面上延伸，其中所述第一电绝缘层具有第一表面迁移，并且所述第一电绝缘层的上表面具有位于所述第一电绝缘层上的第一中空沟沟; 以及在所述第一电绝缘层上形成第二电绝缘层，其中所述第二电绝缘层填充所述第一中空部，并且所述第二电绝缘层的上表面具有位于所述沟槽上的第二中空，所述第二电绝缘层层具有比第一表面迁移小的第二表面迁移。

59. 发明授权

US5476809A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5476809A
公开(公告)日：1995-12-19
申请号：US242085
申请日：1994-05-13
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012 , Y10S438/969
摘要： This invention relates to a semiconductor device which comprises a monocrystalline silicon substrate, a first insulating film formed in a first region on one major surface of the monocrystalline silicon substrate, a first monocrystalline silicon layer formed on the first insulating film, a second insulating film covering a side surface of the first monocrystalline silicon layer, a first polysilicon layer formed to cause a side surface of the first polysilicon layer to contact the second insulating film, and a second monocrystalline silicon layer, having a side surface contacts the first polysilicon layer, formed in a second region of the one major surface of the monocrystalline silicon substrate, and dielectrically isolated from the first monocrystalline silicon layer, and a method of manufacturing the same.
摘要翻译：本发明涉及一种半导体器件，其包括单晶硅衬底，形成在单晶硅衬底的一个主表面上的第一区域中的第一绝缘膜，形成在第一绝缘膜上的第一单晶硅层，第二绝缘膜覆盖层第一单晶硅层的侧表面，形成为使第一多晶硅层的侧表面接触第二绝缘膜的第一多晶硅层和具有与第一多晶硅层接触的侧表面的第二单晶硅层，形成在单晶硅衬底的一个主表面的第二区域中，并且与第一单晶硅层介电隔离，及其制造方法。

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