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51. 发明授权

US06874109B1 Phase shifter with reduced linear dependency 有权
公开(公告)号：US06874109B1
公开(公告)日：2005-03-29
申请号：US09713662
申请日：2000-11-15
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3183 , G01R31/3185
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

52. 发明授权

US06829740B2 Method and apparatus for selectively compacting test responses 有权
标题翻译：用于选择性压实测试响应的方法和装置
公开(公告)号：US06829740B2
公开(公告)日：2004-12-07
申请号：US10354576
申请日：2003-01-29
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R3128
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
摘要翻译：一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

53. 发明授权

US06421794B1 Method and apparatus for diagnosing memory using self-testing circuits 有权
标题翻译：使用自检电路诊断记忆的方法和装置
公开(公告)号：US06421794B1
公开(公告)日：2002-07-16
申请号：US09522279
申请日：2000-03-09
申请人： John T. Chen , Janusz Rajski
发明人： John T. Chen , Janusz Rajski
IPC分类号： H04L122
CPC分类号： G11C29/44 , G11C29/72
摘要： A method and apparatus for diagnosing memory using self—testing circuits. A comparator compares actual data output from a RAM with expected output generated by built—in self—testing (BIST) circuitry. The comparator outputs a resulting initial fail vector which is subsequently input into a compressor. The compressor performs multiple logical operations on the initial fail vector to compress or reduce the bit—width of the initial fail vector, resulting in a compressed fail vector. Once generated, the compressed fail vector is fed to I/O terminals of the integrated circuit (IC) forming a stream of bits to be recorded by test equipment external to the IC. The recorded compressed fail vector is then utilized to reconstruct the initial fail vector that was generated by the bit comparator.
摘要翻译：一种使用自检电路诊断存储器的方法和装置。比较器将RAM的实际数据输出与内置自检（BIST）电路产生的预期输出进行比较。比较器输出随后输入到压缩器中的最终初始故障向量。压缩器对初始故障向量执行多个逻辑运算，以压缩或减小初始故障向量的位宽，导致压缩的失败向量。一旦生成，压缩的故障向量被馈送到集成电路（IC）的I / O端子，形成要由IC外部的测试设备记录的位流。记录的压缩失败向量然后用于重建由位比较器产生的初始故障向量。

54. 发明授权

US5313469A Self-testable digital integrator 失效
标题翻译：自检数字集成商
公开(公告)号：US5313469A
公开(公告)日：1994-05-17
申请号：US75629
申请日：1993-06-11
申请人： Saman Adham , Janusz Rajski , Jerzy Tyszer , Mark Kassab
发明人： Saman Adham , Janusz Rajski , Jerzy Tyszer , Mark Kassab
IPC分类号： G01R31/3183 , G01R31/28
CPC分类号： G01R31/318321
摘要： A self-testable digital integrator comprises binary adding apparatus and storage apparatus. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bias of the digital words fed from the adding apparatus to the storage apparatus. The digital integrator also comprises a second combinational network responsive to the second state of the test mode signal to feed back a carry-out bit of the adding apparatus to a carry-in port of the adding apparatus for test result compaction. The digital integrator optionally comprises a third combinational network responsive to the second state of the test mode signal to feed a carry-out bit of the adding apparatus to the first combinational network, the first combinational network being responsive to the second state of the test mode signal and to the carry-out bit to modify the test pattern signal. The self-testable digital integrator is particularly useful as a component of a digital decimator used to decimate Double Integration Sigma Delta modulation signals.
摘要翻译：一种可自检的数字积分器包括二进制加法装置和存储装置。所述添加装置和所述存储装置在功能上互连，使得所述存储装置将数字字馈送到所述添加装置以添加，并且所述添加装置将所生成的数字字馈送到所述存储装置以进行存储以进行数字集成操作。数字积分器还包括响应于测试模式信号的第一状态的第一组合网络，以将外部输入信号馈送到加法装置以进行积分，并响应于测试模式信号的第二状态馈送到添加装置从从加法装置馈送到存储装置的数字字的选定偏置导出的测试图案信号。数字积分器还包括响应于测试模式信号的第二状态的第二组合网络，以将加法装置的进位位反馈到用于测试结果压缩的加法装置的进位端口。数字积分器可选地包括响应于测试模式信号的第二状态的第三组合网络，以将加法装置的进位位馈送到第一组合网络，第一组合网络响应于测试模式的第二状态信号和进位位修改测试码信号。自检数字积分器作为用于抽取双积分Sigma Delta调制信号的数字抽取器的组件特别有用。

55. 发明授权

US08832512B2 Low power compression of incompatible test cubes 有权
标题翻译：不兼容的测试立方体的低功率压缩
公开(公告)号：US08832512B2
公开(公告)日：2014-09-09
申请号：US13049829
申请日：2011-03-16
申请人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译：公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。可以通过产生低切换控制模式来进一步降低功耗。

56. 发明授权

US08533547B2 Continuous application and decompression of test patterns and selective compaction of test responses 有权
公开(公告)号：US08533547B2
公开(公告)日：2013-09-10
申请号：US13013712
申请日：2011-01-25
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

57. 发明授权

US08499209B2 At-speed scan testing with controlled switching activity 有权
标题翻译：具有受控切换活动的高速扫描测试
公开(公告)号：US08499209B2
公开(公告)日：2013-07-30
申请号：US12765530
申请日：2010-04-22
申请人： Janusz Rajski , Elham K. Moghaddam , Nilanjan Mukherjee , Mark A Kassab , Xijiang Lin
发明人： Janusz Rajski , Elham K. Moghaddam , Nilanjan Mukherjee , Mark A Kassab , Xijiang Lin
IPC分类号： G01R31/28 , G06F11/00 , G06F9/455 , G06F17/50 , G06F11/22
CPC分类号： G01R31/318547 , G01R31/318575
摘要： Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.
摘要翻译：通过用功能背景数据填充测试立方体的未指定位来生成速度扫描测试的测试模式。功能背景数据是当被测电路的开关活动接近稳定状态时观察到的扫描单元值。还公布了EDT（嵌入式确定性测试）环境中的硬件实现。

58. 发明申请

US20110320999A1 DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS 有权
标题翻译：用于测试模式的低功率分解的分解器
公开(公告)号：US20110320999A1
公开(公告)日：2011-12-29
申请号：US13225240
申请日：2011-09-02
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G06F17/50
CPC分类号： G01R31/318547 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

59. 发明申请

US20110231721A1 LOW POWER COMPRESSION OF INCOMPATIBLE TEST CUBES 有权
标题翻译：低功耗压缩不完全测试
公开(公告)号：US20110231721A1
公开(公告)日：2011-09-22
申请号：US13049829
申请日：2011-03-16
申请人： DARIUSZ CZYSZ , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： DARIUSZ CZYSZ , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
IPC分类号： G06F11/00 , G06F1/32
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译：公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。可以通过产生低切换控制模式来进一步降低功耗。

60. 发明申请

US20110055646A1 FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT 审中-公开
标题翻译：记忆环境中的故障诊断
公开(公告)号：US20110055646A1
公开(公告)日：2011-03-03
申请号：US12678747
申请日：2008-09-18
申请人： Nilanjan Mukherjee , Artur Pogiel , Janusz Rajski , Jerzy Tyszer
发明人： Nilanjan Mukherjee , Artur Pogiel , Janusz Rajski , Jerzy Tyszer
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/56 , G11C29/40 , G11C29/44 , G11C29/56008 , G11C2029/1208
摘要： Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feed-back structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter (211), a failing column indicator (213), and/or a failing row indicator (214) to collect memory location information for a failing test response.
摘要翻译：公开的是用于在存储器内置自检环境中暂时压缩失败存储器测试的测试响应签名的方法和设备，以提供即使在多个时间相关存储器的检测中进行存储器内置自检操作的能力测试失败。在本发明的一些实施方案中，将压实的测试响应签名与存储器位置信息一起提供给自动测试设备设备。根据本发明的各种实施方式，具有嵌入式存储器（204）和存储器BIST控制器（206）的集成电路还包括用作签名寄存器的线性反馈结构（410），其可以临时压缩来自在内存测试的测试步骤中的嵌入式存储器阵列。在各种实现中，集成电路还可以包括故障字计数器（211），故障列指示器（213）和/或故障行指示器（214），以收集故障测试响应的存储器位置信息。

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