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51. 发明申请

US20080270049A1 SYSTEM AND METHOD FOR MONITORING RELIABILITY OF A DIGITAL SYSTEM 失效
标题翻译：用于监测数字系统可靠性的系统和方法
公开(公告)号：US20080270049A1
公开(公告)日：2008-10-30
申请号：US11742018
申请日：2007-04-30
申请人： Dae Ik KIM , Jonghae KIM , Moon Ju KIM , James R. MOULIC , Hong Hua SONG
发明人： Dae Ik KIM , Jonghae KIM , Moon Ju KIM , James R. MOULIC , Hong Hua SONG
IPC分类号： G01R31/00
CPC分类号： G01R31/31937 , G01R31/31725
摘要： System and method are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades past a specified threshold. The technique includes implementing a ring oscillator sensor in association with the digital system, wherein logic and/or device percent composition of the ring oscillator sensor mirrors percent composition thereof within the digital system. Counter logic is coupled to the ring oscillator sensor for converting outputted count signals to an oscillation frequency, and control logic is coupled to the counter logic for periodically evaluating oscillation frequency of the ring oscillator sensor and generating a warning signal indicative of reliability degradation if at least one of: (i) a measured or estimated oscillation frequency is below a warning threshold frequency; or (ii) a measured or estimated rate of change in a difference between measured oscillation frequencies exceeds an acceptable rate of change threshold.
摘要翻译：提供系统和方法用于连续监视数字系统的可靠性或老化，并且如果数字系统操作降低到指定的阈值以上，则发出警告信号。该技术包括实现与数字系统相关联的环形振荡器传感器，其中环形振荡器传感器的逻辑和/或设备百分比组成反映数字系统内的其组成的百分比。计数器逻辑耦合到环形振荡器传感器，用于将输出的计数信号转换为振荡频率，并且控制逻辑耦合到计数器逻辑，用于周期性评估环形振荡器传感器的振荡频率，并产生指示可靠性降级的警告信号，如果至少以下之一：（i）测量或估计的振荡频率低于警告阈值频率; 或者（ii）所测量的振荡频率之间的测量或估计的变化率超过可接受的变化率阈值。

52. 发明申请

US20080260296A1 HETEROGENEOUS IMAGE PROCESSING SYSTEM 有权
标题翻译：异构图像处理系统
公开(公告)号：US20080260296A1
公开(公告)日：2008-10-23
申请号：US11738711
申请日：2007-04-23
申请人： William H. Chung , Moon J. Kim , James R. Moulic , Toshiyuki Sanuki
发明人： William H. Chung , Moon J. Kim , James R. Moulic , Toshiyuki Sanuki
IPC分类号： G06K9/54
CPC分类号： G06T1/20
摘要： The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion.
摘要翻译：本发明涉及机器视觉计算环境，更具体地涉及一种用于使用多核处理器系统选择性地加速图像处理应用的执行的系统和方法。在这种情况下，多核处理器系统通常被定义为多平台的，并且可能通过网络或其他连接分布。本发明提供了一种用于执行图像处理应用的机器视觉系统和方法，这里称为图像协处理器，其包括（尤其是）多个多核处理器（MCP），其工作以加速方式处理多个图像。

53. 发明申请

US20080253437A1 MONITORING RELIABILITY OF A DIGITAL SYSTEM 有权
标题翻译：监测数字系统的可靠性
公开(公告)号：US20080253437A1
公开(公告)日：2008-10-16
申请号：US11733318
申请日：2007-04-10
申请人： Dae Ik KIM , Jonghae KIM , Moon Ju KIM , James R. MOULIC , Hong Hua SONG
发明人： Dae Ik KIM , Jonghae KIM , Moon Ju KIM , James R. MOULIC , Hong Hua SONG
IPC分类号： H04B17/00
CPC分类号： G06F11/008
摘要： Method, system and article of manufacture are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades to or past a specified threshold. The technique includes periodically determining a maximum frequency of operation of the digital system, and generating a warning signal indicative of a reliability degradation of the digital system if at least one of: (i) a measured or estimated maximum frequency of operation of the digital system is below a warning threshold frequency of operation of the digital system, wherein the warning threshold frequency is greater than or equal to a manufacturer specified minimum frequency of operation for the digital system; or (ii) a rate of change in the difference between measured maximum frequencies of operation of the digital system exceeds an acceptable rate of change threshold for the digital system.
摘要翻译：提供了方法，系统和制造品，用于连续监视数字系统的可靠性或老化，并且如果数字系统操作降低到或超过指定阈值，则发出警告信号。该技术包括周期性地确定数字系统的最大操作频率，以及产生指示数字系统的可靠性劣化的警告信号，如果以下至少一个：（i）数字系统的测量或估计的最大操作频率低于数字系统的警告阈值操作频率，其中警告阈值频率大于或等于制造商规定的数字系统的最小操作频率; 或者（ii）数字系统的测量的最大操作频率之间的差异的变化率超过数字系统的可接受的变化率阈值。

54. 发明授权

US07418368B2 Method and system for testing processor cores 有权
标题翻译：用于测试处理器内核的方法和系统
公开(公告)号：US07418368B2
公开(公告)日：2008-08-26
申请号：US11624329
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
IPC分类号： G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

55. 发明申请

US20080178023A1 METHOD AND SYSTEM FOR INDEPENDENT PROCESSOR VOLTAGE SUPPLY 有权
标题翻译：独立处理器电压供应方法与系统
公开(公告)号：US20080178023A1
公开(公告)日：2008-07-24
申请号：US11624333
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于通过控制每个核心的单个电源来选择性地调整多核处理器核心电源电压的多核处理器芯片结构，以确保一个或多个内核按照一个时钟速率运行或更多性能规格。标称电源电压被提供给第一处理核心，并且大于或低于标称电源电压的第二核心电源电压被提供给第二处理核心，两个核心都遵守参考时钟速率规范。第二电源电压可以从通过逐渐降低标称电源电压而导出的有序的离散电源电压中选择，可选地，其中所选择的电源电压还使得第二磁芯能够在另一性能规范内操作。

56. 发明申请

US20080104609A1 SYSTEM AND METHOD FOR LOAD BALANCING DISTRIBUTED SIMULATIONS IN VIRTUAL ENVIRONMENTS 审中-公开
标题翻译：虚拟环境中负载平衡分布式仿真的系统与方法
公开(公告)号：US20080104609A1
公开(公告)日：2008-05-01
申请号：US11553178
申请日：2006-10-26
申请人： Bruce D. D'Amora , James R. Moulic , Ashwini K. Nanda
发明人： Bruce D. D'Amora , James R. Moulic , Ashwini K. Nanda
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06N3/006
摘要： A device comprises two or more nodes for processing a simulation of a virtual interactive environment. The two or more nodes comprising at least one component to determine workload amongst at least a first node and a second node the two or more nodes. The at least one component further delegates work to the second node when the workload on the first node exceeds a predetermined boundary, and accepts work from the second node when the workload on the second node is within the predetermined boundary.
摘要翻译：一种设备包括用于处理虚拟交互环境的仿真的两个或多个节点。所述两个或多个节点包括至少一个组件以确定至少第一节点和第二节点之间的两个或更多节点的工作负载。当第一节点上的工作负载超过预定边界时，至少一个组件进一步将工作委托给第二节点，并且当第二节点上的工作负载在预定边界内时，从第二节点接受工作。

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