专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20070033316A1 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US20070033316A1
公开(公告)日：2007-02-08
申请号：US11543878
申请日：2006-10-06
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/36
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

52. 发明授权

US07152130B2 Bus system for use with information processing apparatus 失效
公开(公告)号：US07152130B2
公开(公告)日：2006-12-19
申请号：US11032051
申请日：2005-01-11
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

53. 发明授权

US07102259B2 Rotor of a synchronous induction electric motor 有权
标题翻译：同步感应电动机的转子
公开(公告)号：US07102259B2
公开(公告)日：2006-09-05
申请号：US10292505
申请日：2002-11-13
申请人： Hitoshi Kawaguchi , Yoshio Takita , Hayato Yoshino
发明人： Hitoshi Kawaguchi , Yoshio Takita , Hayato Yoshino
IPC分类号： H02K1/26 , H02K1/22 , H02K19/02
CPC分类号： H02K1/246 , H02K1/22 , H02K1/32 , H02K15/0012 , H02K17/165
摘要： A rotor of a synchronous induction electric motor according to the present invention includes a slot for generating induction torque and a slit for generating reluctance torque. The slot and the slit are filled up with aluminum which is short-circuited by an end-ring at each of both ends of the rotor, and the slit includes a non-filling part penetrating in the direction of the rotational axis and not filled up with the aluminum.
摘要翻译：根据本发明的同步感应电动机的转子包括用于产生感应转矩的槽和用于产生磁阻转矩的缝。槽和狭缝填充有铝，该铝在转子两端的端部由端环短路，并且狭缝包括沿旋转轴线的方向穿透而不填充的不填充部分与铝。

54. 发明授权

US6098159A Information processing apparatus 失效
公开(公告)号：US6098159A
公开(公告)日：2000-08-01
申请号：US84254
申请日：1998-05-26
申请人： Hitoshi Kawaguchi , Koichi Kimura , Hideki Kamimaki , Takayuki Tamura , Kazushi Kobayashi
发明人： Hitoshi Kawaguchi , Koichi Kimura , Hideki Kamimaki , Takayuki Tamura , Kazushi Kobayashi
IPC分类号： G06F12/00 , G06F1/10 , G06F1/12 , G06F13/16 , G11C11/401 , G11C11/407 , G06F13/14
CPC分类号： G06F13/1689
摘要： An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

55. 发明授权

US6098136A Multiple bus system using a data transfer unit 失效
标题翻译：多总线系统使用数据传输单元
公开(公告)号：US6098136A
公开(公告)日：2000-08-01
申请号：US375356
申请日：1999-08-17
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/40 , G06F13/14 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controlling connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接，其控制分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

56. 发明授权

US6008563A Reluctance motor and compressor-driving reluctance motor 失效
标题翻译：磁阻电机和压缩机驱动磁阻电机
公开(公告)号：US6008563A
公开(公告)日：1999-12-28
申请号：US116265
申请日：1998-07-16
申请人： Kazuhiko Baba , Hitoshi Kawaguchi , Yoshio Takita , Hayato Yoshino
发明人： Kazuhiko Baba , Hitoshi Kawaguchi , Yoshio Takita , Hayato Yoshino
IPC分类号： H02K3/48 , H02K1/14 , H02K3/52 , H02K9/00 , H02K19/10 , H02K1/16 , H02K3/46
CPC分类号： H02K3/522 , H02K1/146 , H02K19/103 , H02K9/00
摘要： Winding holding means 8 for retaining windings 6 are respectively provided at axially opposite end portions of each pole protrusion 5 of a stator on the inner peripheral side of the pole protrusions.
摘要翻译：用于保持绕组6的绕线保持装置8分别设置在极突起的内周侧上的定子的每个极突出部5的轴向相对端部。

57. 发明授权

US5915120A Information processing apparatus having a power management system that dynamically changes operating conditions based upon dynamically selected user preferential order setting 失效
标题翻译：具有电源管理系统的信息处理设备，其基于动态选择的用户优先顺序设置来动态地改变操作条件
公开(公告)号：US5915120A
公开(公告)日：1999-06-22
申请号：US855447
申请日：1997-05-13
申请人： Hiroshi Wada , Hitoshi Kawaguchi , Masami Yamagishi
发明人： Hiroshi Wada , Hitoshi Kawaguchi , Masami Yamagishi
IPC分类号： G06F1/00 , G06F1/04 , G06F1/28 , G06F1/32 , H02J7/00
CPC分类号： G06F1/3203
摘要： In an information processing apparatus having a central processing unit, input/output units controlled by the central processing unit such as a liquid crystal display, a hard disk drive, a PCMCIA controller and a floppy disk drive, and a battery for supplying power to the central processing unit and the input/output units, a desired operating time of the information processing apparatus is set in a desired operating time setting circuit. Next, a residual capacity detecting circuit detects a residual capacity of the battery. On the basis of the desired operating time set by the desired operating time setting circuit and an operable time of the information processing apparatus calculated from the residual capacity of the battery detected by the residual capacity detecting circuit, the central processing unit commands an operating condition changing circuit to change operating conditions such that the desired operating time becomes longer than the operable time. The operating condition changing circuit controls power consumption in the input/output units such that the changed operating conditions are met, thus ensuring the desired operable time of the information processing apparatus to be realized.
摘要翻译：在具有中央处理单元的信息处理设备中，由诸如液晶显示器，硬盘驱动器，PCMCIA控制器和软盘驱动器的中央处理单元控制的输入/输出单元，以及用于向中央处理单元和输入/输出单元，信息处理设备的期望操作时间被设置在期望的操作时间设置电路中。接下来，剩余容量检测电路检测电池的剩余容量。基于由期望的操作时间设置电路设置的期望操作时间和根据由剩余容量检测电路检测到的电池的剩余容量计算出的信息处理设备的可操作时间，中央处理单元命令操作条件改变电路以改变操作条件，使得期望的操作时间变得比可操作时间长。操作条件改变电路控制输入/输出单元中的功率消耗，使得满足改变的操作条件，从而确保实现信息处理设备的期望的可操作时间。

58. 发明授权

US5751976A Bus system for use with information processing apparatus 失效
公开(公告)号：US5751976A
公开(公告)日：1998-05-12
申请号：US601993
申请日：1996-02-15
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

59. 发明授权

US5317747A Multiprocessor system and interruption control device for controlling interruption requests between processors and peripheral devices in the multiprocessor system 失效
标题翻译：多处理器系统和中断控制装置，用于控制多处理器系统中的处理器和外围设备之间的中断请求
公开(公告)号：US5317747A
公开(公告)日：1994-05-31
申请号：US666066
申请日：1991-03-07
申请人： Tetsuya Mochida , Kouichi Okazawa , Kouichi Kimura , Hitoshi Kawaguchi , Kazushi Kobayashi
发明人： Tetsuya Mochida , Kouichi Okazawa , Kouichi Kimura , Hitoshi Kawaguchi , Kazushi Kobayashi
IPC分类号： G06F13/24 , G06F9/46 , G06F15/16
CPC分类号： G06F13/24
摘要： An interruption control device for controlling interruption requests in a multiprocessor system having a plurality of processor elements and a plurality of peripheral devices. The interruption control device is connected between the processor elements and the peripheral devices. The interruption control device includes a plurality of interruption request registers for indicating the occurrence of an interruption request from either a processor element or a peripheral device to a processor element and a plurality of interruption enable registers for authorizing an interruption request of a processor element. The interruption request registers are read by the processor element being interrupted to identify the source of the interruption request.
摘要翻译：一种用于控制具有多个处理器元件和多个外围设备的多处理器系统中的中断请求的中断控制装置。中断控制装置连接在处理器元件和外围设备之间。中断控制装置包括用于指示从处理器元件或外围设备到处理器元件的中断请求的发生的多个中断请求寄存器以及用于授权处理器元件的中断请求的多个中断使能寄存器。中断请求寄存器被处理器元件中断，以识别中断请求的源。

60. 发明授权

US5276818A Bus system for information processing system and method of controlling the same 失效
标题翻译：信息处理系统总线系统及其控制方法
公开(公告)号：US5276818A
公开(公告)日：1994-01-04
申请号：US512810
申请日：1990-04-20
申请人： Koichi Okazawa , Hiroaki Aotsu , Hitoshi Kawaguchi , Masami Jikihara , Kazushi Kobayashi , Koichi Kimura , Tetsuya Mochida
发明人： Koichi Okazawa , Hiroaki Aotsu , Hitoshi Kawaguchi , Masami Jikihara , Kazushi Kobayashi , Koichi Kimura , Tetsuya Mochida
IPC分类号： G06F13/28 , G06F13/36 , G06F13/364 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4217 , G06F13/364
摘要： A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.
摘要翻译：一种用于信息处理系统的总线系统，其中在公共总线上控制多个模块之间的数据传输。响应于来自模块的总线使用请求，发出用于中止由具有较低优先级的另一模块执行的数据传输的命令。正在传送数据的模块通过发出一个指示要传送的字是最终字的信号来响应中止命令。通过与从总线控制器提供的时钟同步的与数据具有相同宽度的地址总线，在主机和从机之间传送数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式