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51. 发明授权

US11188106B2 Low-noise high efficiency bias generation circuits and method 有权
公开(公告)号：US11188106B2
公开(公告)日：2021-11-30
申请号：US16744027
申请日：2020-01-15
申请人： pSemi Corporation
发明人： Tae Youn Kim , Robert Mark Englekirk
IPC分类号： G05F1/56 , H03F1/30 , G05F1/46
摘要： An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.

52. 发明授权

US11171631B2 Programmable voltage variable attenuator 有权
公开(公告)号：US11171631B2
公开(公告)日：2021-11-09
申请号：US16240483
申请日：2019-01-04
申请人： pSemi Corporation
发明人： Peter Bacon
IPC分类号： H03H11/24
摘要： A programmable voltage variable attenuator (VVA) that enables selection among multiple analog, continuous attenuation ranges. Some embodiments include a dual-mode interface to enable digitally programming a DAC and provide the analog output to control the attenuation level of the VVA, or alternatively apply an externally provided analog voltage to directly control the VVA attenuation level. A VVA may be used in conjunction with a digital step attenuator (DSA). Some embodiments include circuitry for changing the VVA reference impedance. The attenuator architecture of the VVA includes one or more variable resistance shunt elements and/or series elements which may be a resistor and FET circuit controlled by a provided variable analog voltage. The multiple resistance element architecture may be implemented with stacked FET devices. Embodiments for the VVA may be based, for example, on T-type, Bridged-T type, Pi-type, L-pad type, reflection type, or balanced coupler type attenuators.

53. 发明授权

US11146173B1 Startup of power converter with switched-capacitor circuit 有权
公开(公告)号：US11146173B1
公开(公告)日：2021-10-12
申请号：US17017129
申请日：2020-09-10
申请人： pSemi Corporation
发明人： Carlos Zamarreno Ramos
IPC分类号： G05F1/10 , G05F3/02 , H02M3/07 , H02M1/36 , H02M1/00
摘要： Startup charge balancing circuits and methods for capacitive charge pumps that avoid large in-rush currents and resulting voltage spikes. Embodiments include a charge balance circuit coupled to a corresponding charge pump capacitor of a charge pump. The charge balance circuit includes a comparator that compares the output voltage of the charge pump to a feedback voltage derived from the voltage across the corresponding charge pump capacitor. In response, either a constant current source or a constant current sink is coupled to the charge pump capacitor. Current sourcing or sinking continues until the voltage across the corresponding charge pump capacitor approximates a target voltage, at which point the comparator output toggles, which results in uncoupling of the coupled current source or current sink from the corresponding charge pump capacitor. Embodiments only need one current sink and one current source per charge pump capacitor, and charge balancing is independent of leakage currents.

54. 发明授权

US11133669B2 Adjustable power limiter with integrated power detector 有权
公开(公告)号：US11133669B2
公开(公告)日：2021-09-28
申请号：US16580886
申请日：2019-09-24
申请人： pSemi Corporation
发明人： Jianhua Lu , Hojung Ju
IPC分类号： H02H9/04 , H02H1/00 , H02H9/00
摘要： A limiter having a more ideal limiting function, a short response time, and an adjustable limiting threshold. In one embodiment, a self-activating limiter stack is coupled between circuit ground and a signal line between a source and a receiver. The limiter stack limits the power from the source when the voltage on the signal line exceeds the breakdown voltage of the limiter stack. The threshold of the limiter stack is controlled in part by a first control voltage applied to a control input. A rectifying power detector circuit connected between a node on the signal line and the control input of the limiter stack provides a second control voltage as a function of the signal power at the node. The combined first and second control voltages are applied to the control input to modulate the ON resistance of the limiter stack, thereby limiting the leakage power reaching the protected receiver.

55. 发明授权

US11128261B2 Constant Vds1 bias control for stacked transistor configuration 有权
公开(公告)号：US11128261B2
公开(公告)日：2021-09-21
申请号：US16264106
申请日：2019-01-31
申请人： pSemi Corporation
发明人： Tero Tapio Ranta , Christopher C. Murphy , Jeffrey A. Dykstra
IPC分类号： H03F3/04 , H03F1/22 , H03F3/16 , H03F3/195 , H03F1/56 , H03F3/213 , H03F1/32 , H03F1/30 , H03F1/02 , H03F3/193
摘要： Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.

56. 发明授权

US11075661B1 Method and apparatus to optimize power clamping 有权
公开(公告)号：US11075661B1
公开(公告)日：2021-07-27
申请号：US16808315
申请日：2020-03-03
申请人： pSemi Corporation
发明人： Rong Jiang , Khushali Shah , Peter Bacon
IPC分类号： H04B1/18 , H03F3/189 , H03K5/08 , G05F1/59 , H03H7/24 , H03G3/30 , H03H7/38 , H03G1/00
摘要： A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

57. 发明授权

US11075604B2 RF frequency multiplier without balun 有权
公开(公告)号：US11075604B2
公开(公告)日：2021-07-27
申请号：US16584720
申请日：2019-09-26
申请人： pSemi Corporation
发明人： John Birkbeck
IPC分类号： H03B19/00 , H03D7/14 , H04B1/40
摘要： Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.

58. 发明授权

US11641196B2 High-speed switch with accelerated switching time 有权
公开(公告)号：US11641196B2
公开(公告)日：2023-05-02
申请号：US17677292
申请日：2022-02-22
申请人： pSemi Corporation
发明人： Chengkai Luo
IPC分类号： H03K17/04 , H03K17/0412 , H03K17/693
摘要： A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.

59. 发明授权

US11624762B2 Phase-change material switches 有权
公开(公告)号：US11624762B2
公开(公告)日：2023-04-11
申请号：US17351651
申请日：2021-06-18
申请人： pSemi Corporation
发明人： Jaroslaw Adamski , Jeffrey A. Dykstra , Edward Nicholas Comfoltey
IPC分类号： G01R27/08 , H01L45/00
摘要： Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the resistive heater(s) in a PCM switch to reduce parasitic capacitance caused by the proximity of the resistive heater(s) to the PCM region of a PCM switch. Variations in the resistance of the resistive heater(s) of a PCM switch are mitigated or eliminated by sensing the actual resistance of the resistive heater(s) and then determining a suitable adjusted electrical pulse profile for the resistive heater(s) that generates a precise thermal pulse to the PCM region, thereby reliably achieving a desired switch state while extending the life of the resistive heater(s) and the phase-change material.

60. 发明授权

US11614759B2 Leakage compensation circuit 有权
公开(公告)号：US11614759B2
公开(公告)日：2023-03-28
申请号：US17396508
申请日：2021-08-06
申请人： pSemi Corporation
发明人： Robert Mark Englekirk
IPC分类号： G05F1/56 , G05F1/565 , G05F3/26
摘要： Circuits and methods that compensate for the problems created by low-dropout regulator (LDO) leakage current, particularly when stressed. Embodiments include an improved LDO configured to provide a load current, and which includes a leakage current compensation circuit. The leakage current compensation circuit generates a compensating current that offsets the leakage current through the pass device of the LDO during conditions that induce such leakage. More specifically, the leakage current compensation circuit can replicate the leakage current of the pass device of the LDO and feed a compensating current back into the LDO from a current mirror circuit while drawing zero-power during normal use, when leakage current is absent. LDO circuits that include a leakage current compensation circuit are particularly useful as voltage sources for positive or negative charge pumps, but are also quite useful in applications requiring a regulated voltage output.

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