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51. 发明申请

US20090055668A1 Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design 有权
标题翻译：用于检测流水线电子电路设计中的时钟门控机会的方法和装置
公开(公告)号：US20090055668A1
公开(公告)日：2009-02-26
申请号：US11842491
申请日：2007-08-21
申请人： Matthew Earl Fernsler , Hans Mikael Jacobson , Johny Srouji , Todd Swanson
发明人： Matthew Earl Fernsler , Hans Mikael Jacobson , Johny Srouji , Todd Swanson
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/3867 , Y02D10/128
摘要： A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
摘要翻译：管道电子电路和设计方法通过模拟来识别流水线各阶段之间的时钟门控机会，从而在管线的阶段实现功率节省。在一个实施例中，模拟结果帮助设计者设计流水线电子电路，以通过在模拟识别的时钟选通机会位置处在流水线的各个阶段之间并入时钟选通电路来实现功率守恒。

52. 发明申请

US20090052345A1 Method and Apparatus for an Adapter in a Network Device to Discover its Adapter Name in a Network System 失效
标题翻译：网络设备中适配器的方法和装置，用于在网络系统中发现其适配器名称
公开(公告)号：US20090052345A1
公开(公告)日：2009-02-26
申请号：US11842447
申请日：2007-08-21
申请人： Aaron C. Brown , Scott M. Carlson , Kevin J. Gildea , Roger G. Hathorn , Jeffrey W. Palm , Renato J. Recio
发明人： Aaron C. Brown , Scott M. Carlson , Kevin J. Gildea , Roger G. Hathorn , Jeffrey W. Palm , Renato J. Recio
IPC分类号： H04L12/28
CPC分类号： H04L49/35 , H04L41/12 , H04L49/351 , H04L49/357
摘要： A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a “Fibre Channel over Ethernet” communication capability and methodology. Device driver software manages a Fibre Channel to Ethernet and Ethernet to Fibre Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.
摘要翻译：网络系统支持多种网络通信协议。在一个实施例中，网络设备驱动程序软件提供“以太网光纤通道”通信能力和方法。设备驱动程序软件实时管理光纤通道到以太网和以太网到光纤通道地址转换，以实现网络系统中的数据包通信。所公开的网络系统的不同实施例包括一起提供多个适配器名称发现方法的多个名称服务器和网络设备驱动程序软件。在一个实施例中，适配器名称发现方法包括端口名称发现和适配器属性发现。

53. 发明申请

US20090049456A1 LIMITING RECEIPT OF UNSOLICITED EVENTS BY A LOGICAL PARTITION IN A DATA STORAGE SYSTEM 审中-公开
标题翻译：限制通过数据存储系统中的逻辑分区接收非特定事件
公开(公告)号：US20090049456A1
公开(公告)日：2009-02-19
申请号：US11837887
申请日：2007-08-13
申请人： Brian D. Clark , Juan A. Coronado , Beth A. Peterson
发明人： Brian D. Clark , Juan A. Coronado , Beth A. Peterson
IPC分类号： G06F9/44
CPC分类号： G06F9/455 , G06F9/5072 , G06F9/542
摘要： A logical partition (LPAR) is managed in a data processing system by performing an initial program load (IPL), commencing execution of an application on the LPAR and selecting from a plurality of unsolicited events of which the application is to receive notice. A command is transmitted to a storage controller indicating the identity of the selected unsolicited events, wherein the storage controller will store the information in a data structure. Upon the later occurrence of an unsolicited event, the storage controller will transmit to the LPAR only notices of the selected unsolicited events.
摘要翻译：在数据处理系统中通过执行初始程序加载（IPL）来管理逻辑分区（LPAR），开始在LPAR上执行应用程序，并从应用程序将要接收通知的多个未经请求的事件进行选择。将命令发送到指示所选择的非请求事件的身份的存储控制器，其中存储控制器将信息存储在数据结构中。在稍后发生未经请求的事件之后，存储控制器将只向LPAR发送所选择的非请求事件的通知。

54. 发明申请

US20090049228A1 AVOIDING FAILURE OF AN INITIAL PROGRAM LOAD IN A LOGICAL PARTITION OF A DATA STORAGE SYSTEM 有权
公开(公告)号：US20090049228A1
公开(公告)日：2009-02-19
申请号：US11837880
申请日：2007-08-13
申请人： Brian D. Clark , Juan A. Coronado , Beth A. Peterson
发明人： Brian D. Clark , Juan A. Coronado , Beth A. Peterson
IPC分类号： G06F17/30
CPC分类号： G06F9/45533 , G06F9/4401
摘要： An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure.

55. 发明申请

US20090031180A1 Method for Discovering and Isolating Failure of High Speed Traces in a Manufacturing Environment 审中-公开
标题翻译：发展和隔离制造环境中高速轨迹故障的方法
公开(公告)号：US20090031180A1
公开(公告)日：2009-01-29
申请号：US11828649
申请日：2007-07-26
申请人： Brian James Cagno , Gregg Steven Lucas , Thomas Stanley Truman
发明人： Brian James Cagno , Gregg Steven Lucas , Thomas Stanley Truman
IPC分类号： G06F11/07
CPC分类号： H04L41/0659 , G06F11/076 , H04L41/0803 , H04L41/0866 , H04L43/0823 , H04L43/50
摘要： A mechanism is provided for discovering and isolating failure of high speed traces in a manufacturing environment. The mechanism utilizes transmit pre-emphasis and receiver equalization in combination with attenuated wrap plugs to enhance discovery and isolation of manufacturing defects in the manufacturing environment. The mechanism adjusts pre-emphasis and equalization in real time in high speed devices, allowing for much greater variation to compensate for design margins and specification variances. While the card is under test with wrap-backs installed, the pre-emphasis and receiver equalization are brought to the limits while logging the bit error rate to a non-volatile memory element. The mechanism then compares the bit error rate information to empirically derived signatures for failure isolation.
摘要翻译：提供了用于发现和隔离制造环境中高速迹线故障的机制。该机制采用发射预加重和接收机均衡结合衰减的外壳，以增强制造环境中制造缺陷的发现和隔离。该机制在高速设备中实时调整预加重和均衡，允许更大的变化来补偿设计余量和规格差异。当卡被安装的环绕测试时，预加重和接收器均衡在将误码率记录到非易失性存储器元件时被带到极限。该机制然后将误码率信息与经验派生的签名进行比较，以进行故障隔离。

56. 发明申请

US20090027242A1 HIGH-RATE RLL ENCODING 有权
标题翻译：高速RLL编码
公开(公告)号：US20090027242A1
公开(公告)日：2009-01-29
申请号：US12185095
申请日：2008-08-03
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , G11B20/1426 , G11B2020/1446 , G11B2020/1473 , G11B2220/90 , G11B2220/956
摘要： An unencoded m-bit data input sequence is divided into a block of n bits and a block of m-n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.
摘要翻译：未编码的m位数据输入序列被分成n位块和m-n位块。 n位的块被划分为第一组n + 1个编码比特，其中第一组的P1个子块中的至少一个满足G，M和I约束。第一组n + 1个编码比特被映射到n + 1编码比特的第二组，其中第二组的P2子块中的至少一个在1 /（1 + D2）预编码之后产生至少Q1个转换。第二组n + 1编码比特被分成P3编码子块，并且P3编码子块在（mn）/ s个未编码符号之间进行交织，以形成第（m + 1）比特的输出序列码字，然后存储在数据存储介质。

57. 发明申请

US20080294881A1 METHOD AND APPARATUS FOR INSTRUCTION COMPLETION STALL IDENTIFICATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：信息处理系统中指示完成标识的方法和装置
公开(公告)号：US20080294881A1
公开(公告)日：2008-11-27
申请号：US11753005
申请日：2007-05-24
申请人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
发明人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.
摘要翻译：信息处理系统包括在软件应用程序内执行多个指令或指令线程的处理器。信息处理系统包括在多任务环境中管理处理器系统硬件和软件的操作系统软件。在一个实施例中，操作系统管理指令完成失速分析软件以确定指令停顿的原因或原因。在另一个实施例中，失速分析软件与操作系统软件配合，以在应用程序执行时以每个指令为基础存储指令完成失速事件数据。操作系统软件可以与失速分析软件配合以将指令完成失速数据存储在存储器中以供系统用户或其他软件稍后操作。

58. 发明申请

US20080286701A1 METHOD FOR KINETICALLY CONTROLLED ETCHING OF COPPER 失效
标题翻译：用于动态控制铜蚀刻的方法
公开(公告)号：US20080286701A1
公开(公告)日：2008-11-20
申请号：US11749800
申请日：2007-05-17
申请人： David L. Rath , Emanuel I. Cooper
发明人： David L. Rath , Emanuel I. Cooper
IPC分类号： G03C5/58 , C09K13/00
CPC分类号： H01L21/32134 , C23F1/14 , C23F1/18 , C23F1/34
摘要： An etching composition, particularly for kinetically controlled etching of copper and copper alloy surfaces; a process for etching copper and copper alloys, particularly for etching at high rates to provide uniform and smooth, isotropic surfaces; an etched copper or copper alloy surface obtained by the process; and a process for generating copper or copper alloy electrical interconnects or contact pads. The etching composition and etching processes provide a smooth, isotropic fast etch of copper and copper alloys for semiconductor fabrication and packaging.
摘要翻译：蚀刻组合物，特别用于铜和铜合金表面的动态控制蚀刻; 蚀刻铜和铜合金的方法，特别是用于高速蚀刻以提供均匀和光滑的各向同性表面的方法; 通过该方法获得的蚀刻铜或铜合金表面; 以及用于产生铜或铜合金电互连或接触焊盘的工艺。蚀刻组合物和蚀刻工艺提供用于半导体制造和封装的铜和铜合金的平滑，各向同性的快速蚀刻。

59. 发明申请

US20080256345A1 Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System 失效
标题翻译：当处理器在信息处理系统中遇到低置信度时通过调节指令获取来节省电力的方法和装置
公开(公告)号：US20080256345A1
公开(公告)日：2008-10-16
申请号：US11733589
申请日：2007-04-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3844 , G06F1/3203 , G06F9/3802 , G06F9/3806
摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要翻译：一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。当处理器可能正确预测分支指令的结果时，获取操作将返回全速。

60. 发明申请

US20080251888A1 Method and Apparatus for Self-Contained Automatic Decoupling Capacitor Switch-Out in Integrated Circuits 失效
标题翻译：集成电路中自包含自动去耦电容开关的方法和装置
公开(公告)号：US20080251888A1
公开(公告)日：2008-10-16
申请号：US11733435
申请日：2007-04-10
申请人： Vikas Agarwal , Asit S. Ambekar , Sanjay Dubey , Saiful Islam
发明人： Vikas Agarwal , Asit S. Ambekar , Sanjay Dubey , Saiful Islam
IPC分类号： H01L27/02
CPC分类号： H01L27/0805 , G06F1/26 , H01L27/0629 , Y10T307/865
摘要： An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines.
摘要翻译：集成电路（IC）包括耦合到电源的电源互连。集成电路包括执行所需功能的电子器件，还包括在整个集成电路中提供降噪的去耦电容器电路。在一个实施例中，每个去耦电容器电路包括去耦电容器和开关电路。当开关电路检测到没有实质的去耦电容器泄漏时，开关电路在连接模式期间将去耦电容器连接到电源互连。然而，当开关电路检测到实质的去耦电容器泄漏时，开关电路在断开模式期间有效地将去耦电容器与电源互连件断开。去耦电容电路在连接模式下自我初始化，无需外部控制信号，因此是独立的。由于去耦电容电路的自包含性质，集成电路可能包含一个去耦电容电路的阵列，而不需要相应的去耦电容器控制线的大量芯片空间。

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