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41. 发明授权

US11057033B2 Hybrid power module 有权
公开(公告)号：US11057033B2
公开(公告)日：2021-07-06
申请号：US16504908
申请日：2019-07-08
申请人： Cree, Inc.
发明人： Edward Robert Van Brunt , Adam Barkley , Sei-Hyung Ryu , Zachary Cole , Kraig J. Olejniczak
IPC分类号： H03K17/567 , H03K17/693 , H03K17/76 , H01L29/16 , H03K17/62
摘要： A power module includes a plurality of power semiconductor devices. The plurality of power semiconductor devices includes an insulated gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) coupled in parallel between a first power switching terminal and a second power switching terminal. The IGBT and the MOSFET are silicon carbide devices. By providing the IGBT and the MOSFET together, a tradeoff between forward conduction current and reverse conduction current of the power module, the efficiency, and the specific current rating of the power module may be improved. Further, providing the IGBT and the MOSFET as silicon carbide devices may significantly improve the performance of the power module.

42. 发明授权

US10951109B2 Line commutated converters 有权
公开(公告)号：US10951109B2
公开(公告)日：2021-03-16
申请号：US16491446
申请日：2018-03-05
申请人： GENERAL ELECTRIC TECHNOLOGY GMBH
发明人： Robert Stephen Whitehouse , Carl David Barker
IPC分类号： H02M1/084 , H02M7/155 , H03K17/76
摘要： In the field of line commutated converters, for use in high voltage direct current (HVDC) power transmission, a line commutated converter comprises a plurality of converter limbs that extend between first and second DC terminals. Each converter limb includes first and second limb portions which are separated by an AC terminal. The first limb portions together define a first limb portion group and the second limb portions together define a second limb portion group. Each limb portion includes at least one switching element that is configured to turn on and conduct current when it is forward biased and it receives a turn on signal and to naturally turn off and no longer conduct current when it is reverse biased and the current flowing through it falls to zero. The converter also includes a control unit.

43. 发明申请

US20210028783A1 High Throw-Count RF Switch 有权
公开(公告)号：US20210028783A1
公开(公告)日：2021-01-28
申请号：US16989462
申请日：2020-08-10
申请人： pSemi Corporation
发明人： Eric S. Shapiro , Payman Shanjani
IPC分类号： H03K17/693 , H04B1/04 , H04B1/48 , H03K17/62 , H03K17/76
摘要： A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

44. 发明申请

US20170230049A1 High Throw-Count RF Switch 有权
公开(公告)号：US20170230049A1
公开(公告)日：2017-08-10
申请号：US15019882
申请日：2016-02-09
申请人： Peregrine Semiconductor Corporation
发明人： Eric S. Shapiro , Payman Shanjani
IPC分类号： H03K17/693 , H03K17/62 , H03K17/76
CPC分类号： H03K17/693 , H03K17/62 , H03K17/76 , H03K2017/066 , H04B1/0458 , H04B1/48 , H04B2001/485
摘要： A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

45. 发明授权

US09048840B2 20V to 250V high current ASIC PIN diode driver 有权
标题翻译： 20V至250V大电流ASIC PIN二极管驱动器
公开(公告)号：US09048840B2
公开(公告)日：2015-06-02
申请号：US13330858
申请日：2011-12-20
申请人： Chengxin Liu , Christopher D. Weigand , Richard J. Giacchino , Scott Vasquez
发明人： Chengxin Liu , Christopher D. Weigand , Richard J. Giacchino , Scott Vasquez
IPC分类号： H03K3/00 , H03K17/74 , H03K17/76 , H03K3/356
CPC分类号： H03K17/74 , H03K3/356182 , H03K17/76
摘要： An integrated circuit including a first circuit, a second circuit, a third circuit, a first complementary pair of transistors, and a second complementary pair of transistors. The first circuit may be configured to generate a first input signal in response to a first control input signal. The second circuit may be configured to generate a first output signal and a second output signal in response to the first input signal and a bias signal. The third circuit may be configured to generate the bias signal in response to a bias input signal. The first complementary pair of transistors may be configured to drive a first series output of the integrated circuit in response to the first output signal. The second complementary pair of transistors may be configured to drive a first shunt output of the integrated circuit in response to the second output signal.
摘要翻译：一种集成电路，包括第一电路，第二电路，第三电路，第一互补对晶体管和第二互补晶体管对。第一电路可以被配置为响应于第一控制输入信号而产生第一输入信号。第二电路可以被配置为响应于第一输入信号和偏置信号而产生第一输出信号和第二输出信号。第三电路可以被配置为响应偏置输入信号产生偏置信号。第一互补晶体管对可以被配置为响应于第一输出信号来驱动集成电路的第一串联输出。第二互补晶体管对可以被配置为响应于第二输出信号来驱动集成电路的第一分流输出。

46. 发明授权

US08884650B2 High-frequency semiconductor switching circuit 有权
标题翻译：高频半导体开关电路
公开(公告)号：US08884650B2
公开(公告)日：2014-11-11
申请号：US13741999
申请日：2013-01-15
申请人： Panasonic Corporation
发明人： Takahito Miyazaki
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177 , G06F7/38 , H01L21/70 , H03K17/567 , H03K17/76 , H03K19/00
CPC分类号： H03K19/0013 , H03K17/567 , H03K17/76
摘要： A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages.
摘要翻译：本发明的二极管开关逻辑电路被配置为：使公共输入输出端子和各个输入 - 输出端子之间的路径中的至少一个变成导通状态; 控制端子的控制电压分别施加到路径切换FET级的栅极; 控制端子的控制电压的逻辑合成电压分别施加到并联FET级的栅极; 并且每个逻辑合成电压由施加到一个并联FET级的控制电压的逻辑否定和分别施加到其余分流FET级的控制电压的逻辑和的逻辑积产生。

47. 发明授权

US07038523B2 Voltage trimming circuit 失效
标题翻译：电压调整电路
公开(公告)号：US07038523B2
公开(公告)日：2006-05-02
申请号：US10681647
申请日：2003-10-08
申请人： Jung Pill Kim , Jungwon Suh
发明人： Jung Pill Kim , Jungwon Suh
IPC分类号： H03K17/76
CPC分类号： G11C29/021 , G11C5/147 , G11C29/02 , G11C29/028
摘要： Methods and circuits for minimizing or eliminating the effect of trimming circuits in a voltage generating circuit are provided. In general, the effects of channel resistance of switches of the trimming circuit are reduced by utilizing switches in series with the output, rather than in parallel with resistors, as in conventional trimming circuits. Because the switches are not in parallel with the resistors, when the switches are turned on, no channel resistance is added to the effective resistance controlled by the trimming circuit.
摘要翻译：提供了用于最小化或消除电压产生电路中的微调电路的影响的方法和电路。通常，通过利用与输出串联的开关，而不是与传统的微调电路中的电阻并联，减小了微调电路的开关的沟道电阻的影响。由于开关不与电阻并联，因此当开关导通时，由修整电路控制的有效电阻不会增加通道电阻。

48. 发明授权

US5969561A Integrated circuit having a variable RF resistor 失效
标题翻译：具有可变RF电阻的集成电路
公开(公告)号：US5969561A
公开(公告)日：1999-10-19
申请号：US035368
申请日：1998-03-05
申请人： Michael E. McGillan
发明人： Michael E. McGillan
IPC分类号： H03H11/24 , H03K17/62 , H03K17/76 , H04B1/48 , H03K5/08
CPC分类号： H03H11/24 , H03K17/6221 , H03K17/76 , H04B1/48
摘要： A bipolar radio frequency (RF) integrated circuit having a functional equivalent of a PIN diode. The RF integrated circuit includes a low frequency lateral PNP transistor having an emitter having a P+ region, a collector having a P+ region, a base having an N+ region and an N region having a current dependent stored charge having a relatively low level when no current is flowing between the emitter and a junction connecting the base and collector. An RF resistance between the emitter and the junction is controlled by a bias applied from the emitter to the junction. By varying the bias, the low frequency lateral PNP transistor from the emitter to the junction is used as a variable RF resistor or as an RF signal carrying component in a variable attenuator or RF switch.
摘要翻译：具有PIN二极管功能等效的双极射频（RF）集成电路。 RF集成电路包括具有P +区域的发射极，具有P +区域的集电极，具有N +区域的基极和具有电流相关存储电荷的N区域的低频横向PNP晶体管，当没有电流时具有相对低的电平在发射极和连接基极和集电极的连接点之间流动。发射极和结之间的RF电阻由从发射极到结的施加的偏置来控制。通过改变偏置，从发射极到结的低频横向PNP晶体管用作可变RF电阻器，或者用作可变衰减器或RF开关中的RF信号承载元件。

49. 发明授权

US5932936A Switch matrix 失效
标题翻译：开关矩阵
公开(公告)号：US5932936A
公开(公告)日：1999-08-03
申请号：US32786
申请日：1998-03-02
申请人： Andreas Potthast , Georg Rauh
发明人： Andreas Potthast , Georg Rauh
IPC分类号： G01R33/3415 , H01Q3/24 , H01Q3/40 , H03K17/00 , H03K17/76 , H02B1/24
CPC分类号： H03K17/76 , H01Q3/24 , H01Q3/40 , H03K17/002 , G01R33/3415 , Y10T307/74 , Y10T307/747
摘要： A switch matrix has a set of inputs, a set of outputs, controllable switch elements and a conductor arrangement that is connected to the inputs and outputs and to the controllable switch elements. The controllable switch elements together with the conductor arrangement produce switched electrical connection paths between at least two inputs and an output. The electrical connection paths contain connecting branches that, proceeding from the at least two inputs and the output, meet at a junction point. The connecting branches connected to the at least two inputs have identical electrical lengths up to the junction point.
摘要翻译：开关矩阵具有一组输入，一组输出，可控开关元件和连接到输入和输出以及可控开关元件的导体布置。可控开关元件与导体布置一起在至少两个输入和输出之间产生开关电连接路径。电连接路径包含从至少两个输入端和输出端在连接点处相交的连接分支。连接到至少两个输入的连接分支具有相同的电长度直到连接点。

50. 发明授权

US5781059A Driver circuit for semiconductor test system 失效
标题翻译：半导体测试系统的驱动电路
公开(公告)号：US5781059A
公开(公告)日：1998-07-14
申请号：US716996
申请日：1996-09-20
申请人： Hiroyuki Shiotsuka
发明人： Hiroyuki Shiotsuka
IPC分类号： G01R31/28 , G01R31/319 , H03K17/76 , H03K19/00 , H03K19/0175 , H03K17/62
CPC分类号： H03K17/76 , G01R31/31924
摘要： A driver circuit for a semiconductor test system generates test signals having predetermined voltage levels without being affected by stray capacitances. The driver circuit includes: a buffer amplifier for supplying test signals having predetermined voltage levels; a first diode bridge connected to a first voltage source for providing a first voltage level to the buffer amplifier where the first diode bridge has an upper node and an lower; a second diode bridge connected to a second voltage source for providing a second voltage level to the buffer amplifier where the second diode bridge has an upper node and an lower node; a third diode bridge connected to a third voltage source for providing a third voltage level to the buffer amplifier where the third diode bridge has an upper node and an lower node; a fourth diode bridge connected between the first voltage source and the lower node of the third diode bridge; and a fifth diode bridge connected between the second voltage source and the upper node of the third diode bridge.
摘要翻译：用于半导体测试系统的驱动器电路产生具有预定电压电平的测试信号，而不受杂散电容的影响。驱动器电路包括：用于提供具有预定电压电平的测试信号的缓冲放大器; 连接到第一电压源的第一二极管桥，用于向缓冲放大器提供第一电压电平，其中第一二极管桥具有上节点和下电平; 连接到第二电压源的第二二极管桥，用于向缓冲放大器提供第二电压电平，其中第二二极管桥具有上节点和下节点; 连接到第三电压源的第三二极管电桥，用于向缓冲放大器提供第三电压电平，其中第三二极管电桥具有上部节点和下部节点; 第四二极管桥连接在第三二极管桥的第一电压源和下部节点之间; 以及连接在第二电压源和第三二极管桥的上部节点之间的第五二极管桥。

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