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41. 发明授权

US5414302A Semiconductor device with a multilayered contact structure having a boro-phosphate silicate glass planarizing layer 失效
标题翻译：具有多孔接触结构的半导体器件，其具有硼磷酸盐硅酸盐玻璃平坦化层
公开(公告)号：US5414302A
公开(公告)日：1995-05-09
申请号：US188113
申请日：1994-01-28
申请人： Yun-seung Shin , Sung-nam Chang
发明人： Yun-seung Shin , Sung-nam Chang
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/485 , H01L27/10 , H01L23/48 , H01L29/10 , H01L29/44 , H01L29/52
CPC分类号： H01L21/76802 , H01L23/485 , H01L24/05 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/13091
摘要： A high-density semiconductor memory device has a self-aligning contact structure for electrical connection between lower and upper conductive layers, and an inter-insulating layer with a via for forming the contact structure. The contact structure has a contact pad including a first conductive layer electrically connected with the lower conductive layer within the via and formed on a predetermined portion of the inter-insulating layer around the groove, a planarizing material filling up the groove formed on the first conductive layer, and second conductive layers formed on the planarizing material and exposed first conductive layer.
摘要翻译：高密度半导体存储器件具有用于下导电层和上导电层之间的电连接的自对准接触结构，以及具有用于形成接触结构的通孔的绝缘层。所述接触结构具有接触焊盘，所述接触焊盘包括与所述通路内的所述下导电层电连接并形成在所述槽周围的所述绝缘层的预定部分上的第一导电层，填充形成在所述第一导电层和形成在平坦化材料上并暴露的第一导电层的第二导电层。

42. 发明授权

US5412248A Semiconductor device package with shaped parts for direct coupling to standard connectors 失效
标题翻译：具有成形部件的半导体器件封装，用于直接耦合到标准连接器
公开(公告)号：US5412248A
公开(公告)日：1995-05-02
申请号：US960529
申请日：1992-10-13
申请人： Bruno Murari , Giuseppe Libretti
发明人： Bruno Murari , Giuseppe Libretti
IPC分类号： H01L23/04 , B60R16/02 , H01L23/31 , H01L23/32 , H01R13/52 , H01R13/66 , H01R31/06 , H01L23/48 , H01L29/41 , H01L29/52 , H01L29/60
CPC分类号： B60R16/02 , H01L23/3107 , H01R13/665 , H01R31/06 , H01L2924/0002 , H01R13/5219
摘要： A packaging structure is disclosed for a semiconductor device, having a body configured to include at least one part provided with contact terminals and shaped to form a connector member for direct coupling to a standard connector member from an external circuit. A connector assembly is also disclosed which is fully sealed from moisture and comprises the packaging structure.
摘要翻译：公开了一种用于半导体器件的封装结构，其具有被配置为包括设置有接触端子的至少一个部分的主体并成形为形成用于从外部电路直接耦合到标准连接器构件的连接器构件。还公开了一种连接器组件，其从湿气完全密封并且包括该包装结构。

43. 发明授权

US5402006A Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound 失效
标题翻译：半导体器件具有增强的散热器和导线与塑料模具之间的粘合性
公开(公告)号：US5402006A
公开(公告)日：1995-03-28
申请号：US973894
申请日：1992-11-10
申请人： Bobby O'Donley
发明人： Bobby O'Donley
IPC分类号： H01L23/373 , H01L23/433 , H01L23/28 , H01L23/48 , H01L29/44 , H01L29/52
CPC分类号： H01L23/4334 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L24/48 , H01L2924/00014 , H01L2924/01029 , H01L2924/01046 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/3011
摘要： A semiconductor device (10) includes a semiconductor die (18) and a heat spreader (16) adjacent the semiconductor die (18) for carrying heat away from the semiconductor die (18). The heat spreader (16) has a copper core (30) and a cupric oxide coating (32) formed on at least a portion of the core (30). A plastic package (12) is molded onto the semiconductor die (18) and the heat spreader (16) for supporting the semiconductor die (18) and the heat spreader (16). The cupric oxide coating (32) enhances adhesion of the heat spreader (16) to the plastic package (12).
摘要翻译：半导体器件（10）包括半导体管芯（18）和邻近半导体管芯（18）的散热器（16），用于将热量从半导体管芯（18）传送出去。散热器（16）具有形成在芯部（30）的至少一部分上的铜芯（30）和氧化铜涂层（32）。塑料封装（12）被模制到半导体管芯（18）和用于支撑半导体管芯（18）和散热器（16）的散热器（16）上。氧化铜涂层（32）增强了散热器（16）与塑料封装（12）的粘合性。

44. 发明授权

US5394012A Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US5394012A
公开(公告)日：1995-02-28
申请号：US136064
申请日：1993-10-14
申请人： Hiroshi Kimura
发明人： Hiroshi Kimura
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/04 , H01L27/10 , H01L27/108 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L27/10852 , H01L21/28512 , H01L27/10861 , H01L28/82
摘要： Source/drain diffusion regions are formed at a surface of a silicon substrate, which is substantially flat and has a first surface roughness. Surfaces of the source/drain diffusion regions are covered with a polysilicon film having a surface which has a second surface roughness larger than the first surface roughness. The polysilicon film is removed by etching to expose the surfaces of the source/drain diffusion regions. Owing to this etching for removal, the surfaces of the source/drain diffusion regions have a third surface roughness larger than the first surface roughness.
摘要翻译：源极/漏极扩散区域形成在硅衬底的基本上平坦且具有第一表面粗糙度的表面上。源极/漏极扩散区的表面被具有第二表面粗糙度大于第一表面粗糙度的表面的多晶硅膜覆盖。通过蚀刻去除多晶硅膜以暴露源极/漏极扩散区域的表面。由于该蚀刻用于去除，源极/漏极扩散区域的表面具有大于第一表面粗糙度的第三表面粗糙度。

45. 发明授权

US5384487A Off-axis power branches for interior bond pad arrangements 失效
标题翻译：离轴电源分支用于内部接合焊盘布置
公开(公告)号：US5384487A
公开(公告)日：1995-01-24
申请号：US58120
申请日：1993-05-05
申请人： Michael D. Rostoker , Nicholas F. Pasch , Joe Zelayeta
发明人： Michael D. Rostoker , Nicholas F. Pasch , Joe Zelayeta
IPC分类号： H01L23/485 , H01L23/50 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L24/06 , H01L23/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351
摘要： A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads. Constraining the location of the power-carrying bond pads to an interior area of the die approximately one half of the die area, and substantially centered about the axis, keeps longitudinal thermal displacements of the ends of leadframe fingers or bond wires connected to the power-carrying bond pads relatively small compared to those experienced in peripheral bond pad placement (at the die edges), and ensures shorter, more direct internal paths to circuitry on the die.
摘要翻译：一种用于改善对半导体管芯的功率分配的同时降低半导体器件组件中的接合焊盘上的热诱导机械应力的技术是通过沿着管芯的轴线以共线布置提供信号承载接合焊盘来实现的，在离轴位置承载接合焊盘。信号承载接合焊盘的轴上构造使接合焊盘相对于轴的横向热位移最小化，这使引线框架指或接合线的任何纵向，压缩端移动最小化，从而最小化接合焊盘界面的热致机械应力去死功率承载接合垫离轴的定位减少了将管芯上的电路连接到功率承载接合焊盘所需的内部（针对芯片）布线的长度。将功率承载接合焊盘的位置限制在模具的内部区域中大约是模具区域的一半，并且基本上围绕轴线居中，保持引线框架指状物的端部或连接到电源接合焊盘的接合线的纵向热位移，与在外围接合焊盘放置（在模具边缘）处经历的相比，承载焊盘相对较小，并确保对芯片上的电路的更短，更直接的内部路径。

46. 发明授权

US5381037A Lead frame with selected inner leads coupled to an inner frame member for an integrated circuit package assemblies 失效
标题翻译：引线框架与选定的内引线相连，用于集成电路封装组件的内框架构件
公开(公告)号：US5381037A
公开(公告)日：1995-01-10
申请号：US71414
申请日：1993-06-03
申请人： Jerry Olivarez
发明人： Jerry Olivarez
IPC分类号： H01L23/04 , H01L23/12 , H01L23/48 , H01L23/495 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/49503 , H01L23/49541 , H01L23/49558 , H01L2224/05553 , H01L2224/48247 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/30107
摘要： A high performance hermetic integrated circuit package assembly for housing an integrated circuit die wherein the package assembly affords substantially reduced ground bounce within the integrated circuit. The package assembly includes a lead frame of electrically conductive material having a first predetermined pattern of outer leads and a second predetermined pattern of, integrally connected, inner leads for providing interconnection to the die through a plurality of contact pads thereon, a series of electrically conductive wires connecting selected ones of the contact pads to selected ones of the inner leads, a base for mounting the die and includes a first layer of glass for supporting the lead frame and, a cap with a second layer of glass for reacting with the first layer of glass to provide a hermetic enclosure for the die. The lead frame further includes a frame interconnection member at the ends of the outer leads for interconnecting all the outer leads and an inner frame member which includes an annular rectangle of electrically conductive material for interconnecting all inner ground leads for reducing the electrical inductances and resistances of the ground leads and for providing mechanical strength to the lead frame. A carrier ring disposed around the outer leads for providing mechanical stability and testability, and a plurality of spaced tie bar members extending integrally between the inner frame member and the frame interconnection member to allow for multi-stage trimming and forming of the outer leads from the carrier ring.
摘要翻译：一种用于容纳集成电路管芯的高性能封闭集成电路封装组件，其中所述封装组件在所述集成电路内提供显着减小的接地反弹。封装组件包括导电材料的引线框架，其具有第一预定图案的外引线和第二预定图案的整体连接的内引线，用于通过其上的多个接触焊盘提供与管芯的互连，一系列导电将选定的接触焊盘连接到所选择的内部引线中的导线，用于安装模具的基座，并且包括用于支撑引线框架的第一玻璃层和具有用于与第一层反应的第二玻璃层的盖子的玻璃以提供用于模具的密封外壳。引线框架还包括在外引线的端部处的用于互连所有外引线的框架互连构件，以及内框架构件，其包括导电材料的环形矩形，用于互连所有内部接地引线以减小电感和电阻接地引线并为引线框架提供机械强度。设置在外引线周围的用于提供机械稳定性和可测试性的载体环，以及多个间隔开的连接杆构件，其一体地延伸在内框架构件和框架互连构件之间，以允许从第一和第二构件的多个阶段修整和形成外引线载体环。

47. 发明授权

US5373192A Electromigration resistance metal interconnect 失效
标题翻译：电镀金属互连
公开(公告)号：US5373192A
公开(公告)日：1994-12-13
申请号：US936060
申请日：1992-08-28
申请人： Koji Eguchi
发明人： Koji Eguchi
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/5226 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , Y10S438/927
摘要： A semiconductor device is provided which includes a conductive layer, an insulating film formed on the surface of the conductive layer, and a conductive metal interconnection layer formed on the insulating film and electrically connected to the conductive layer through a contact hole formed in a predetermined position of the insulating film. The conductive metal interconnection and the surface of the conductive layer are directly joined together and a silicon layer including a single crystal or polycrystalline silicon having a grain size of at least about 10 .mu.m is interposed between the conductive metal interconnection layer and the insulating film. The conductive metal interconnection layer becomes a single crystal or a polycrystal having a grain size of about 10 .mu.m or above under the influence of the crystalline properties of the underlying crystal of the silicon layer. Therefore, in the conductive metal interconnection layer in the entire region including the inside portion of the contact hole, essentially no grain boundaries exist. Thus, electromigration of conductive metal ions is controlled.
摘要翻译：提供了一种半导体器件，其包括导电层，形成在导电层的表面上的绝缘膜，以及形成在绝缘膜上并通过形成在预定位置的接触孔电连接到导电层的导电金属互连层的绝缘膜。导电金属互连和导电层的表面直接接合在一起，并且包括具有至少约10μm的晶粒尺寸的单晶或多晶硅的硅层插入在导电金属互连层和绝缘膜之间。在硅层的下面的晶体的结晶性质的影响下，导电性金属互连层成为具有约10μm以上的晶粒尺寸的单晶或多晶体。因此，在包括接触孔的内部的整个区域的导电性金属配线层中，基本上不存在晶界。因此，控制导电金属离子的电迁移。

48. 发明授权

US5355004A Semiconductor integrated circuit device having wiring for clock signal supply 失效
标题翻译：具有用于时钟信号供给的布线的半导体集成电路器件
公开(公告)号：US5355004A
公开(公告)日：1994-10-11
申请号：US975275
申请日：1992-11-12
申请人： Mutsuo Saitoh
发明人： Mutsuo Saitoh
IPC分类号： H01L21/82 , H01L21/822 , H01L23/528 , H01L27/04 , H01L49/00 , H01L23/48 , H01L29/44 , H01L29/52
CPC分类号： H01L23/528 , H01L2924/0002
摘要： A semiconductor integrated circuit device wherein terminals other than clock signal terminals in circuit blocks are connected via a first wiring layer to a clock signal source and only the clock signal terminals in the blocks are connected via a second wiring layer to the source. The second wiring layer is formed above the first wiring layer and is connected to the clock signal terminals. Since the second wiring layer is dedicated to the clock signal, clock signal wiring can be laid out as desired when a layout is designed by a hierarchical design technique. There is no chance that propagation characteristics of the clock signals to the blocks deviates, and a cell area can be reduced. Preferably, a third wiring layer connected to the second wiring layer is furthermore provided for dedication to the clock signal.
摘要翻译：一种半导体集成电路器件，其中除了电路块中的时钟信号端子之外的端子经由第一布线层连接到时钟信号源，并且仅块中的时钟信号端子经由第二布线层连接到源极。第二布线层形成在第一布线层的上方，与时钟信号端子连接。由于第二布线层专用于时钟信号，当通过分层设计技术设计布局时，时钟信号布线可根据需要布置。不存在时钟信号对块的传播特性偏离的可能性，并且可以减小单元区域。优选地，还提供连接到第二布线层的第三布线层用于致力于时钟信号。

49. 发明授权

US5321304A Detecting the endpoint of chem-mech polishing, and resulting semiconductor device 失效
标题翻译：检测化学机械抛光的终点，得到半导体器件
公开(公告)号：US5321304A
公开(公告)日：1994-06-14
申请号：US033832
申请日：1993-03-19
申请人： Michael D. Rostoker
发明人： Michael D. Rostoker
IPC分类号： B24B37/013 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： B24B37/013
摘要： A contact structure is formed atop a semiconductor wafer at a level whereat it is desired to terminate polishing of a layer overlying the contact structure. When the contact structure becomes exposed to a polishing slurry, an electrical characteristic, such as resistance or impedance, is registered by measuring apparatus. In one embodiment, two or more contact structures are formed atop the wafer, vias are formed through the wafer, and the vias are filled, thereby providing a conductive path from the contact structures to the back side of the wafer. The measuring apparatus probes the filled vias on the back side of the wafer. A change in resistance/impedance indicates that the contact structures have become exposed during polishing, and polishing is terminated. In another embodiment of the invention, one or more contact structures are formed atop the wafer. The measuring apparatus is connected to a probe in the polishing slurry, and to the wafer itself, such as to the back side of the wafer. Again, a change in resistance/impedance indicates that the contact structures have become exposed during polishing, and polishing is terminated.
摘要翻译：接触结构形成在半导体晶片的上方，其处于期望终止覆盖接触结构的层的抛光的水平。当接触结构暴露于抛光浆料时，通过测量装置记录诸如电阻或阻抗的电特性。在一个实施例中，在晶片顶部形成两个或更多个接触结构，通孔通过晶片形成，并且通孔被填充，从而提供从接触结构到晶片背面的导电路径。测量装置探测晶片背面的填充通孔。电阻/阻抗的变化表示接触结构在抛光期间已经暴露，并且抛光终止。在本发明的另一个实施例中，在晶片顶部形成一个或多个接触结构。测量装置连接到抛光浆料中的探针，以及晶片本身，如晶片的背面。再次，阻抗/阻抗的变化表明接触结构在抛光过程中已经暴露，并且抛光被终止。

50. 发明授权

US5317188A Means for and methods of testing automated tape bonded semiconductor devices 失效
标题翻译：用于测试自动化胶带半导体器件的方法和方法
公开(公告)号：US5317188A
公开(公告)日：1994-05-31
申请号：US874628
申请日：1992-04-27
申请人： Kenji Kondou
发明人： Kenji Kondou
IPC分类号： H01L21/60 , G01R31/28 , H01L21/66 , H01L23/495 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/49572 , G01R31/2831 , G01R31/2853 , H01L2924/0002
摘要： A semiconductor device produced by a TAB method is provided which comprises a carrier tape section having a device hole, a first wiring layer formed on one surface of a tape section to be used for assembling the semiconductor device, a semiconductor chip retained in the device-hole electrically connected the first wiring layer, and a second wiring layer formed on the other surface of the tape section for electrically connecting the first wiring layer of the semiconductor device to the first wiring layer of a semiconductor device adjacently disposed thereto before being cut. By clamping the tape section on the widthwise sides with an electroconductive member pair electrically connected to each other, the first and second wiring layers are electrically connected. By disposing the electroconductive member pair in such a manner that is shown above to each of a plurality of semiconductor devices formed on the tape, these semiconductor devices can be electrically connected to the second wiring layer. By applying an electric signal for testing through the second wiring layer to the plurality of semiconductor devices, these devices can be test under such a state that is being formed on the carrier tape. It is preferable to electrically connect the first wiring layer to second wiring layer through through-holes formed in the tape.
摘要翻译：提供了一种通过TAB方法制造的半导体器件，其包括具有器件孔的载带部分，形成在用于组装半导体器件的带部分的一个表面上的第一布线层，保留在器件中的半导体芯片，以及形成在带部分的另一个表面上的第二布线层，用于在切割之前将半导体器件的第一布线层与相邻设置的半导体器件的第一布线层电连接。通过在宽度方向侧夹着带部分，其中彼此电连接的导电构件对，第一和第二布线层电连接。通过将导电构件对以如上所示的方式设置在形成在带上的多个半导体器件中的每一个上，这些半导体器件可以电连接到第二布线层。通过向多个半导体器件施加用于通过第二布线层的测试的电信号，可以在形成在载带上的状态下进行这些装置的测试。优选通过形成在带中的通孔将第一布线层与第二布线层电连接。

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