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41. 发明授权

US10977365B2 Protection of an iterative calculation against horizontal attacks 有权
公开(公告)号：US10977365B2
公开(公告)日：2021-04-13
申请号：US16041077
申请日：2018-07-20
申请人： STMICROELECTRONICS (ROUSSET) SAS
发明人： Ibrahima Diop , Yanis Linge , Pierre-Yvan Liardet
IPC分类号： G06F21/00 , G06F21/55 , G06F21/60 , G06F7/72 , H04L9/00 , G06F21/72
摘要： An iterative calculation is performed on a first number and a second number, while protecting the iterative calculation against side-channel attacks. For each bit of the second number, successively, an iterative calculation routine of the bit of the second number is determined. The determination is made independent of a state of the bit. The determined iterative calculation routine of the bit is executed. A result of the iterative calculation is generated based on a result of the execution of the determined iterative calculation routine of a last bit of the second number.

42. 发明申请

US20210089695A1 LOGIC SIMULATION OF CIRCUIT DESIGNS USING ON-THE-FLY BIT REDUCTION FOR CONSTRAINT SOLVING 有权
公开(公告)号：US20210089695A1
公开(公告)日：2021-03-25
申请号：US17023153
申请日：2020-09-16
申请人： Synopsys, Inc.
发明人： In-Ho Moon
IPC分类号： G06F30/367 , G06F30/327 , G06F9/451 , G06F7/44 , G06F7/72
摘要： A system performs logic simulation of a circuit design specified using a hardware description language such as Verilog. The system performs constraint solving based on an expression specified in the specification of the circuit design. The system identifies required bits for each variable in the expression. The number of required bits is less than the number of bits specified in the variable declaration. The system performs bit-level constraint solving by performing a bit operation on the set of required bits and a simplified processing of the remaining bits of the variable. Since the original circuit design is preserved with the original bit-widths for simulation, those required bits are used on the fly internally during constraint solving. Furthermore, dynamic bit reductions on arithmetic operations are performed on the fly. The system improves computational efficiency by restricting bit operations to fewer bits of variables and operators of the expression.

43. 发明申请

US20210081178A1 PERFORMING CONSTANT MODULO ARITHMETIC 有权
公开(公告)号：US20210081178A1
公开(公告)日：2021-03-18
申请号：US17105210
申请日：2020-11-25
申请人： Imagination Technologies Limited
发明人： Thomas Rose
IPC分类号： G06F7/72
摘要： A binary logic circuit for determining y=x mod(2m−1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer β and a second m-bit integer γ; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by β; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by γ; and the binary value 1.

44. 发明申请

US20210074027A1 IMAGE DATA COMPRESSION 有权
公开(公告)号：US20210074027A1
公开(公告)日：2021-03-11
申请号：US17000694
申请日：2020-08-24
申请人： Imagination Technologies Limited
发明人： Paul Higginbottom , Mark Jackson Pulver , Seyed Ahamed
IPC分类号： G06T9/00 , G06T3/40 , G06F7/72 , G06F7/50
摘要： A method and compression unit for compressing a block of image data to satisfy a target level of compression, wherein the block of image data comprises a plurality of image element values, each image element value comprising one or more data values relating to a respective channel. For each of the channels: (i) an origin value for the channel for the block is determined, (ii) difference values are determined representing differences between the data values and the determined origin value for the channel for the block, and (iii) a first number of bits for losslessly representing a maximum difference value of the difference values for the channel for the block is determined. The determined first number of bits for each of the channels is used to determine a respective second number of bits for each of the channels, the second number of bits being determined such that representing each of the difference values for the channels with the respective second number of bits satisfies the target level of compression for compressing the block of image data. Compressed data is formed, having for each of the one or more channels an indication of the determined origin value for the channel, an indication of the determined first number of bits for the channel, and representations of the determined difference values for the channel, wherein each of the representations of the determined difference values for the channel uses the determined second number of bits for the channel, such that the target level of compression is satisfied.

45. 发明授权

US10924270B2 Secret calculation system, secret calculation apparatus, and secret calculation method 有权
公开(公告)号：US10924270B2
公开(公告)日：2021-02-16
申请号：US15755888
申请日：2016-08-29
申请人： NEC CORPORATION
发明人： Jun Furukawa
IPC分类号： H04L9/08 , G09C1/00 , G06F7/485 , G06F7/544 , G06F7/58 , G06F7/72
摘要： The secret calculation system comprises three secret calculation apparatuses. An ith secret calculation apparatus (i=1, 2, 3) comprises a holder that holds (S[i], T[i]) and (S′[i], T′[i]) as distributed values of an n-bit number W and an n-bit W′ (n is any natural number), respectively; a first multiplicator that derives a logical conjunction of S[i] and S′[i]; a second multiplicator that derives a logical conjunction of T[i] and T′[i]; and a first subtractor that derives a difference between the logical conjunction derived by the first multiplicator and the logical conjunction derived by the second multiplicator.

46. 发明申请

US20200380122A1 ELLIPTIC CURVE POINT MULTIPLICATION OPERATION METHOD AND APPARATUS 审中-公开
公开(公告)号：US20200380122A1
公开(公告)日：2020-12-03
申请号：US16970488
申请日：2019-06-13
申请人： BEIJING SMARTCHiP MICROELECTRONICS TECHNOLOGY COMPANY LIMITED , STATE GRID INFORMATION & TELECOMMUNICATION GROUP CO., LTD , State GRID CORPORATION OF CHINA
发明人： Dongyan ZHAO , Xiaoke TANG , Yanyan YU , Xiaobo HU , Shipirig ZANG , Jie GAN , Liang LIU , zhe ZHANG , Yinzi TU
IPC分类号： G06F21/55 , G06F21/72 , G06F7/72
摘要： Disclosed are an elliptic curve point multiplication operation method and apparatus. The elliptic curve point multiplication operation method comprises ordered point multiplication and point addition operations. In a point addition operation process, when scanning that a current bit of a scalar K is not 0, a true point addition operation is executed, and when scanning that the current bit of the scalar K is 0, an equivalent point conversion operation is executed; the result of the true point addition operation and the result of the equivalent point conversion operation are stored in an identical register file, the register file comprising multiple registers. According to the elliptic curve point multiplication operation method and apparatus, side channel analysis and security error attack can be effectively resisted.

47. 发明申请

US20200274710A1 FINITE-FIELD DIVISION OPERATOR, ELLIPTIC CURVE CRYPTOSYSTEM HAVING FINITE-FIELD DIVISION OPERATOR AND METHOD FOR OPERATING ELLIPTIC CURVE CRYPTOSYSTEM 审中-公开
公开(公告)号：US20200274710A1
公开(公告)日：2020-08-27
申请号：US16717028
申请日：2019-12-17
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： Sang-Woo LEE , Hyeok-Chan KWON
IPC分类号： H04L9/30 , G06F7/72
摘要： Disclosed herein are a finite-field division operator, an elliptic curve cryptosystem having the finite-field division operator, and a method for operating the elliptic curve cryptosystem. The method for operating an elliptic curve cryptosystem may include, setting, by a key setting unit, a length of a key of a cryptographic algorithm, generating, by the key setting unit, first setup information that indicates a number of words corresponding to the key length, and generating, by the key setting unit, second setup information that indicates a number of repetitions of an operation by a finite-field division operator corresponding to the key length.

48. 发明申请

US20200272340A1 TECHNOLOGIES FOR PERFORMING COLUMN ARCHITECTURE-AWARE SCRAMBLING 审中-公开
公开(公告)号：US20200272340A1
公开(公告)日：2020-08-27
申请号：US15930035
申请日：2020-05-12
申请人： Intel Corporation
发明人： Zion Kwok , Jawad Khan , Richard Coulson
IPC分类号： G06F3/06 , G06F7/72
摘要： Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

49. 发明授权

US10756893B2 Elliptic curve random number generation 有权
公开(公告)号：US10756893B2
公开(公告)日：2020-08-25
申请号：US16277017
申请日：2019-02-15
申请人： BlackBerry Limited
发明人： Daniel Richard L. Brown , Scott Alexander Vanstone
IPC分类号： H04L9/08 , G06F7/58 , H04L9/30 , H04L9/06 , G06F7/72
摘要： An elliptic curve random number generator avoids escrow keys by choosing a point on the elliptic curve as verifiably random. An arbitrary string is chosen and a hash of that string computed. The hash is then converted to a field element of the desired field, the field element regarded as the x-coordinate of a point on the elliptic curve and the x-coordinate is tested for validity on the desired elliptic curve. If valid, the x-coordinate is decompressed to the point , wherein the choice of which is the two points is also derived from the hash value. Intentional use of escrow keys can provide for back up functionality. The relationship between P and is used as an escrow key and stored by for a security domain. The administrator logs the output of the generator to reconstruct the random number with the escrow key.

50. 发明申请

US20200266970A1 A COMPUTATION DEVICE AND METHOD 审中-公开
公开(公告)号：US20200266970A1
公开(公告)日：2020-08-20
申请号：US16761865
申请日：2018-10-29
申请人： KONINKLIJKE PHILIPS N.V.
发明人： RONALD RIETMAN , SEBASTIAAN JACOBUS ANTONIUS DE HOOGH
IPC分类号： H04L9/00 , G06F7/72 , G06F7/76 , H04L9/08
摘要： Some embodiments are directed to an electronic computation device (100) arranged for obfuscated execution of a multiplication. The device comprises a storage (120) arranged for storing multiple variables used in the execution of an arithmetic operation, a variable (x: y; 2) of the multiple variables being represented as multiple multiplicative shares (X=(x0, x1, . . . , xm−1); Y=(y0, y1, . . . , ym−1); 20), said multiplicative shares being represented in the storage as multiple additive shares (xi=(xi,0,xi,1, . . . , xi,n−1); Yi=(yi,0,yi,1, . . . , yi,n−1); 210, 220).

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