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41. 发明授权

US08040976B2 Digital receiver and method 有权
标题翻译：数字接收机和方法
公开(公告)号：US08040976B2
公开(公告)日：2011-10-18
申请号：US11545765
申请日：2006-10-10
申请人： Bradley John Morris , Arthur Thomas Gerald Fuller
发明人： Bradley John Morris , Arthur Thomas Gerald Fuller
IPC分类号： H04L27/00
CPC分类号： H04L27/22 , H03M3/462 , H03M3/47 , H03M7/3028 , H04B1/0007
摘要： A receiver and method is provided for sigma-delta converting an RF signal to a digital signal and downconverting to a digital baseband signal. The RF signal is split into N phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (A/D) sigma-delta converter. Polyphase decimation techniques and demodulation are applied to the phased signals to generate a demodulated digital signal. The demodulated digital signal is further downconverted to the appropriate baseband signal.
摘要翻译：提供了一种接收机和方法，用于将RF信号转换成数字信号并下变频成数字基带信号。 RF信号被分为N个相位，可以使用采样和保持电路实现，并且每个相位被数字化，如可以使用模数（A / D）Σ-Δ转换器所实现的。将多相抽取技术和解调应用于相控信号以产生解调数字信号。解调的数字信号进一步下变频到适当的基带信号。

42. 发明申请

US20100331039A1 INTEGRATED POLY-PHASE FIR FILTER IN DOUBLE-SAMPLED ANALOG TO DIGITAL CONVERTERS 有权
标题翻译：集成多相FIR滤波器在双抽样模拟数字转换器
公开(公告)号：US20100331039A1
公开(公告)日：2010-12-30
申请号：US12495427
申请日：2009-06-30
申请人： Rahmi Hezar
发明人： Rahmi Hezar
IPC分类号： H04L27/06 , H03M3/00 , H04M1/00
CPC分类号： H03M3/47
摘要： A sigma delta analog to digital converter includes a clock operating at a conversion clock rate and first and second conversion paths. The first path includes a first sigma delta modulator configured to produce from an input analog signal a first bit stream at the clock rate, and a first digital filter configured to decimate the first bit stream. The second conversion path has a second sigma delta modulator configured to produce from the input analog signal a second bit stream separate from the first bit stream at the clock rate, and a second digital filter configured to decimate the second bit stream.
摘要翻译： Σ-Δ模数转换器包括以转换时钟速率和第一和第二转换路径工作的时钟。第一路径包括被配置为以时钟速率从输入模拟信号产生第一位流的第一Σ-Δ调制器和被配置为抽取第一位流的第一数字滤波器。第二转换路径具有第二Σ-Δ调制器，其被配置为从输入模拟信号产生以时钟速率与第一比特流分离的第二比特流，以及被配置为抽取第二比特流的第二数字滤波器。

43. 发明授权

US07515084B1 Analog to digital converter using asynchronous pulse technology 有权
标题翻译：模数转换器采用异步脉冲技术
公开(公告)号：US07515084B1
公开(公告)日：2009-04-07
申请号：US11726484
申请日：2007-03-22
申请人： Jose Cruz-Albrecht , Peter Petre , Joseph F. Jensen
发明人： Jose Cruz-Albrecht , Peter Petre , Joseph F. Jensen
IPC分类号： H03M1/60
CPC分类号： H03M3/47 , H03M3/432
摘要： A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.
摘要翻译：数模转换器包括将模拟输入信号转换为异步脉冲序列的时间编码器，将异步脉冲序列转换成并行的脉冲序列流以相对较低速度的脉冲异步DeMUX电路，数字转换器，异步数字到同步数字转换器，用于产生绝对时间基准的定时参考电路和数字信号处理器。该架构提供了基于脉冲编码的模数转换，并具有脉冲编码信号的并行数字化方案。

44. 发明申请

US20080074302A1 Delta-sigma AD converter 失效
标题翻译： Delta-sigma AD转换器
公开(公告)号：US20080074302A1
公开(公告)日：2008-03-27
申请号：US11898645
申请日：2007-09-13
申请人： Taiji Akizuki , Tomoaki Maeda , Hisashi Adachi
发明人： Taiji Akizuki , Tomoaki Maeda , Hisashi Adachi
IPC分类号： H03M1/00
CPC分类号： H03M3/47
摘要： The output of a first integrator is quantized in a quantizer. The quantized signal is subjected to D/A conversion, successively output to a plurality of output paths by a first switching circuit, sampled and held by a plurality of charge-holding circuits of a first feedback circuit, and successively output by a second switching circuit to one of the input terminals of a subtractor. On the other hand, the output signal of the first integrator is successively output by a third switching circuit to a plurality of output paths, sampled and held by a plurality of charge-holding circuits of a second feedback circuit, and successively input to the other input terminal of the subtractor by a fourth switching circuit along with signals held in an input portion, which samples and holds input analog signals. By doing so, a plurality of signals with different sampling timings are integrated accumulatively by the subtractor and the first integrator. When integration functions used to obtain an n-th order noise-shaping effect are multiplexed and operated using a single integrator, the integrator's current consumption can be suppressed.
摘要翻译：在量化器中量化第一积分器的输出。量化信号进行D / A转换，由第一反馈电路的多个电荷保持电路采样和保持的第一开关电路连续地输出到多个输出路径，并由第二开关电路到减法器的输入端之一。另一方面，第一积分器的输出信号由第三开关电路连续地输出到由第二反馈电路的多个电荷保持电路采样和保持的多个输出路径，并连续输入到另一个第四开关电路的减法器的输入端以及保持在输入部分中的信号，其中采样并保持输入的模拟信号。通过这样做，具有不同采样定时的多个信号由减法器和第一积分器累积地积分。当使用用于获得n阶噪声整形效果的积分功能使用单个积分器进行复用和操作时，可以抑制积分器的电流消耗。

45. 发明授权

US07057540B2 Sigma-delta (ΣΔ) analog-to-digital converter (ADC) structure incorporating a direct sampling mixer 有权
标题翻译：结合直接采样混频器的Sigma-delta（SigmaDelta）模数转换器（ADC）结构
公开(公告)号：US07057540B2
公开(公告)日：2006-06-06
申请号：US10273217
申请日：2002-10-17
申请人： Khurram Muhammad , Robert B. Staszewski , Feng Chen , Dirk Leipold
发明人： Khurram Muhammad , Robert B. Staszewski , Feng Chen , Dirk Leipold
IPC分类号： H03M3/00
CPC分类号： H03M3/47 , H03M3/496 , H04B1/1036
摘要： A sigma-delta analog-to-digital converter-offers advantages such as noise shaping and high frequency operation. However, a sampling circuit needed to provide a highly oversampled discrete-time sample stream with low noise characteristics is difficult to design and implement. The present invention provides a sigma-delta mixer 300 with such a sampling circuit 310. The present invention discloses a sampling circuit using switched capacitors 307, 308, and 309 with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream.
摘要翻译： Σ-Δ模数转换器 - 具有噪声整形和高频操作等优点。然而，需要提供具有低噪声特性的高度过采样离散时间采样流所需的采样电路难以设计和实现。本发明提供了具有这种采样电路310的Σ-Δ混合器300。本发明公开了一种使用具有低噪声特性的开关电容器307,308和309的采样电路，同时能够提供高度过采样的离散时间采样流。

46. 发明授权

US07006023B2 Sigma-delta modulator with passive bandpass loop filter 有权
标题翻译：带无源带通环路滤波器的Σ-Δ调制器
公开(公告)号：US07006023B2
公开(公告)日：2006-02-28
申请号：US10661019
申请日：2003-09-12
申请人： Feng Chen
发明人： Feng Chen
IPC分类号： H03M3/00
CPC分类号： H03M3/404 , H03M3/43 , H03M3/456 , H03M3/47
摘要： Digitizing a signal includes sampling and holding an analog signal to yield a sampled signal, where the analog signal includes information. The sampled signal is filtered at a passive filter circuit to yield a filtered signal. The passive filter circuit includes at least one passive element and the filtered signal is characterized by a bandpass response. The filtered signal is quantized to yield a digital signal, where the digital signal corresponds to the analog signal and the digital signal includes the information.
摘要翻译：数字化信号包括采样和保持模拟信号以产生采样信号，其中模拟信号包括信息。采样信号在无源滤波器电路进行滤波以产生滤波信号。无源滤波器电路包括至少一个无源元件，滤波后的信号的特征在于带通响应。经滤波的信号被量化以产生数字信号，其中数字信号对应于模拟信号，并且数字信号包括信息。

47. 发明授权

US06650264B1 Quadrature sampling architecture and method for analog-to-digital converters 有权
标题翻译：模数转换器的正交采样架构和方法
公开(公告)号：US06650264B1
公开(公告)日：2003-11-18
申请号：US09414209
申请日：1999-10-07
申请人： Brian P. Lum Shue Chan , Brian D. Green , Donald A. Kerth
发明人： Brian P. Lum Shue Chan , Brian D. Green , Donald A. Kerth
IPC分类号： H03M300
CPC分类号： H03M1/1215 , H03M3/40 , H03M3/47
摘要： Quadrature sampling architecture and method are disclosed for analog-to-digital converters that provide improved digital output signals over prior quadrature mixing implementations. Sampling circuitry according to the present invention samples an input signal with a first and second sampling signals to produce real and imaginary sampled output signals. The first sampling signal, which is associated with the real sampled output signal, is delayed by one-fourth cycle with respect to the second sampling signal, which is associated with the imaginary sampled output signal. This one-fourth cycle sampling signal difference allows for simplified construction of the sampling circuitry. In addition, filter circuitry according to the present invention processes the real and imaginary digital data output signals so that the imaginary digital data output signal is advanced by one-fourth cycle with respect to the real digital data output signal. This one-fourth cycle relative advance tends to eliminate undesirable magnitude distortion and error signals in complex digital output signals that have been mixed down to baseband. Furthermore, the real and imaginary signal paths may be interchanged and still take advantage of the present invention.
摘要翻译：公开了用于模数转换器的正交采样架构和方法，其在现有的正交混频实现方面提供改进的数字输出信号。根据本发明的采样电路用第一和第二采样信号对输入信号进行采样以产生实数和虚数采样的输出信号。与实际采样输出信号相关联的第一采样信号相对于与虚拟采样输出信号相关联的第二采样信号被延迟四分之一周期。这个四分之一周期采样信号差异允许采样电路的简化结构。此外，根据本发明的滤波器电路处理实数和虚数数字输出信号，使得虚数数字数据输出信号相对于实数数字数据输出信号提前四分之一。这个四分之一周期的相对提前趋向于消除已经被混合到基带的复杂数字输出信号中的不期望的幅度失真和误差信号。此外，实信号路径和虚信号路径可以互换，并且仍然利用本发明。

48. 发明授权

US06608581B1 Superconductor modulator with very high sampling rate for analog to digital converters 有权
标题翻译：超导体调制器具有非常高的模数转换器采样率
公开(公告)号：US06608581B1
公开(公告)日：2003-08-19
申请号：US09883490
申请日：2001-06-19
申请人： Vasili Semenov
发明人： Vasili Semenov
IPC分类号： H03M136
CPC分类号： H03M3/47 , H03M3/43 , H03M3/456
摘要： The invention provides an analog-to-digital modulator for converting an analog input signal to a digital output signal. The filter is constructed and arranged to subtract the feedback signal from the external input signal and to filter the subtracted signal such that the filter output signal is attenuated when the subtracted signal is outside said pass band. A plurality of superconducting comparators and digital-to-analog converters are utilized in a time-interleaved mode. The feedback loop filter, digital-to-analog converters, and superconducting comparators are arranged within a feedback loop such that the filter output signal from the feedback loop filter is communicated to the superconducting comparators such that the comparators generate Single Flux Quantum pulses- at their digital outputs. The pulses are communicated to the digital-to-analog converters and therein converted to analog signals. These signals are in turn combined into an integrated analog signal and communicated via the feedback loop back to the feedback loop filter, thereby effectively improving the resolution of the quantization performed by the comparators. The sampling times of the comparators are arranged such that the sequence in which each comparator samples the analog signal that is applied to its input is different for each comparator. The analog signals at the analog outputs of the digital-to-analog converters are generated and combined into an integrated analog signal such that each digital-to-analog converter contributes a different component of this integrated signal.
摘要翻译：本发明提供了一种用于将模拟输入信号转换为数字输出信号的模拟 - 数字调制器。滤波器被构造和布置成从外部输入信号中减去反馈信号，并对相减信号进行滤波，使得当减法信号在所述通带之外时滤波器输出信号被衰减。多个超导比较器和数模转换器以时间交织的方式被使用。反馈环路滤波器，数模转换器和超导比较器被布置在反馈回路内，使得来自反馈环路滤波器的滤波器输出信号被传送到超导比较器，使得比较器在它们的位置产生单通量量子脉冲数字输出。脉冲被传送到数模转换器，并在其中转换为模拟信号。这些信号又被组合成一个集成的模拟信号，并通过反馈回路传送回反馈环路滤波器，从而有效地提高了比较器执行量化的分辨率。比较器的采样时间被布置成使得每个比较器对应用于其输入的模拟信号进行采样的顺序对于每个比较器是不同的。数模转换器的模拟输出端的模拟信号被生成并组合成一个集成的模拟信号，这样每个数模转换器就可以提供该集成信号的不同分量。

49. 发明授权

US06538588B1 Multi-sampling &Sgr;-&Dgr; analog-to-digital converter 有权
标题翻译：多采样SIGMA-DELTA模数转换器
公开(公告)号：US06538588B1
公开(公告)日：2003-03-25
申请号：US09664989
申请日：2000-09-18
申请人： Seyfollah Bazarjani
发明人： Seyfollah Bazarjani
IPC分类号： H03M300
CPC分类号： H03M3/47 , H03M3/406 , H03M3/418 , H03M3/43 , H03M3/454
摘要： A bandpass &Sgr;&Dgr; ADC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved resonator, or a four-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a &Sgr;&Dgr; ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 &Sgr;&Dgr; ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass &Sgr;&Dgr; ADC can also be used in conjunction with undersampling to provide a frequency downconversion.
摘要翻译：利用单回路或MASH架构的带通SIGMADELTA ADC，其中谐振器被实现为延迟单元谐振器，基于延迟单元的谐振器，前向欧拉谐振器，双路交错谐振器或四路径交错谐振器。谐振器可以用诸如有源RC，gm-C，MOSFET-C，开关电容器或开关电流的模拟电路技术来合成。开关电容器或开关电流电路可以使用单采样，双采样或多采样电路进行设计。使用开关电容电路的SIGMADELTA ADC的非严格要求允许ADC以CMOS工艺实现，以最大限度地降低成本并降低功耗。双采样电路提供改进的匹配和改进的采样时钟抖动容限。特别地，带通MASH 4-4 SIGMADELTA ADC在CDMA应用的过采样比为32时提供了85dB的模拟信噪比。带通SIGMADELTA ADC也可与欠采样一起使用，以提供频率下变频。

50. 发明申请

US20020118128A1 Parallel time interleaved delta sigma modulator 失效
标题翻译：并行时间交错delta-Σ调制器
公开(公告)号：US20020118128A1
公开(公告)日：2002-08-29
申请号：US10005089
申请日：2001-12-05
发明人： Raymond E. Siferd
IPC分类号： H03M003/00
CPC分类号： H03M3/47 , H03M3/406 , H03M3/424 , H03M3/456
摘要： A bandpass analog to digital converter includes M single channel delta sigma modulators having N-bit quantizer outputs arranged in a parallel configuration and operated at a predetermined sample frequency (fs). The modulator outputs are time interleaved and digitally combined in a manner that provides performance characteristics comparable to a modulator with a sample frequency of Mfs. Thus, bandpass center frequencies that are much higher than conventional single channel architectures are achievable. Single channel first order modulator bandpass center frequencies are restricted to fcnullfs/4. However, a range of center frequencies approaching Mfs/2 is supported. This increased frequency capability is obtained while maintaining the delta sigma noise shaping near the higher bandpass center frequencies to reduce the effects of quantization noise. This results in a high signal to noise ratio with a corresponding high resolution at the much higher center frequencies.
摘要翻译：带通模拟到数字转换器包括M个单通道ΔΣ调制器，其具有排列成并联配置并以预定采样频率（fs）操作的N位量化器输出。调制器输出以提供与具有Mfs的采样频率的调制器相当的性能特征的方式进行时间交织和数字组合。因此，可以实现比常规单通道架构高得多的带通中心频率。单通道一阶调制器带通中心频率限制在fc = fs / 4。然而，支持接近Mfs / 2的一系列中心频率。获得增加的频率能力，同时保持较高带通中心频率附近的Δ-Σ噪声整形，以减少量化噪声的影响。这导致在高得多的中心频率处具有相应高分辨率的高信噪比。

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