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41. 发明申请

US20180013445A1 DECODING METHOD, AND MEMORY STORAGE APPARATUS AND MEMORY CONTROL CIRCUIT UNIT USING THE SAME 有权
公开(公告)号：US20180013445A1
公开(公告)日：2018-01-11
申请号：US15236487
申请日：2016-08-15
申请人： EpoStar Electronics Corp.
发明人： Yu-Hua Hsiao , Heng-Lin Yen , Ming-Yu Tsai
IPC分类号： H03M13/11
CPC分类号： H03M13/1128 , H03M13/1105 , H03M13/1108 , H03M13/1111 , H03M13/112 , H03M13/3723 , H03M13/451 , H03M13/6325
摘要： A decoding method for low density parity code is provided. The method includes performing an iterative decoding operation for a codeword, wherein a plurality of Log-Likelihood-Ratios correspond respectively to a plurality of data bits of the codeword; determining whether the iterative decoding operation is successful; determining whether a perturbation condition is met if the iterative decoding operation is not successful; performing protect operation for a first Log-Likelihood-Ratio among the Log-Likelihood-Ratios, and performing a perturbation operation for a plurality of second Log-Likelihood-Ratios among the Log-Likelihood-Ratios, wherein the second Log-Likelihood-Ratios are different to the first Log-Likelihood-Ratio; and re-performing the iterative decoding operation for the codeword after finishing the perturbation operation.

42. 发明申请

US20170222755A1 DECODING MODULE WITH LOGARITHM CALCULATION FUNCTION 审中-公开
公开(公告)号：US20170222755A1
公开(公告)日：2017-08-03
申请号：US15281669
申请日：2016-09-30
申请人： MStar Semiconductor, Inc.
发明人： Yu Hsien KU
IPC分类号： H04L1/00
CPC分类号： H04L1/0045 , H03M13/1102 , H03M13/112 , H03M13/2957 , H03M13/615 , H03M13/6577 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： A decoding module for a communication device includes a first calculation circuit, outputting the larger between a first parameter and a second parameter as a first output parameter; a first arithmetic circuit, calculating a first product of a third parameter and a first slope, and a first difference between a first constant and the first product; a second arithmetic circuit, calculating a second product of the third parameter and a second slope, and a second difference between a second constant and the second product; a second calculation circuit, selecting the largest among a third constant, the first difference and the second difference and generating a second output parameter, wherein the third constant is zero; and an addition circuit, adding the first output parameter and the second output parameter to generate output information, according to which the communication device determines a data bit.

43. 发明申请

US20170063395A1 DESIGN OF DVB-S2 LDPC DECODER USING OVERLAPPED DECODING SCHEME 有权
标题翻译：使用重叠解码方案的DVB-S2 LDPC解码器的设计
公开(公告)号：US20170063395A1
公开(公告)日：2017-03-02
申请号：US15132585
申请日：2016-04-19
申请人： KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
发明人： Jun-Young WI , Jun Heo , Sung Won Kim
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/112 , H03M13/1137 , H03M13/1165
摘要： Provided is a low density parity check decoder, which includes a bit node calculating unit configured to calculate a bit node, a check node calculating unit configured to calculate a check node, a control unit configured to control calculation of the bit node and the check node, and a storage unit configured to store calculation values of the bit node or the check node, wherein the control unit calculates the bit node or the check node so that the node calculations are overlapped, by using an address offset value of the storage unit, thereby reducing a decoding time.
摘要翻译：提供了一种低密度奇偶校验解码器，其包括：被配置为计算比特节点的比特节点计算单元，被配置为计算校验节点的校验节点计算单元，被配置为控制比特节点和校验节点的计算的控制单元以及存储单元，其被配置为存储所述比特节点或所述校验节点的计算值，其中，所述控制单元通过使用所述存储单元的地址偏移值来计算所述比特节点或所述校验节点，使得所述节点计算重叠，从而减少了解码时间。

44. 发明申请

US20170041024A1 METHOD AND APPARATUS FOR REDUCING IDLE CYCLES DURING LDPC DECODING 审中-公开
标题翻译：用于在LDPC解码期间减少空闲周期的方法和装置
公开(公告)号：US20170041024A1
公开(公告)日：2017-02-09
申请号：US15284060
申请日：2016-10-03
申请人： Marvell International Ltd.
发明人： Yuan-Mao Chang , Engling Yeo
IPC分类号： H03M13/11 , H03M13/25 , H03M13/00
CPC分类号： H03M13/112 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/255 , H03M13/3715 , H03M13/616 , H03M13/6337 , H03M13/6508 , H03M13/6561 , H03M13/6577
摘要： There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel.
摘要翻译：根据实施例，提供了一种解码码字的方法，该方法结合定义可变节点和校验节点的低密度奇偶校验（LDPC）码，该方法包括：在数据信道上接收码字; 评估数据通道的质量; 并迭代地更新可变节点的值以解码码字; 其中根据数据信道的评估质量，以不同的数值精度更新可变节点的值。

45. 发明申请

US20160329910A1 NON-BINARY LDPC DECODER USING BINARY SUBGROUP PROCESSING 审中-公开
标题翻译：使用二进制子进程的非二进制LDPC解码器
公开(公告)号：US20160329910A1
公开(公告)日：2016-11-10
申请号：US15150340
申请日：2016-05-09
申请人： Western Digital Technologies, Inc.
发明人： Kasra VAKILINIA , Majid NEMATI ANARAKI , Anantha Raman KRISHNAN
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/1131 , G06F11/10 , H03M13/112 , H03M13/1171 , H03M13/616 , H03M13/658 , H03M13/6583
摘要： In one embodiment, an electronic system includes a decoder configured to decode an encoded data unit using multiple variable nodes and multiple check nodes to perform a low-density parity check (LDPC) decoding process. The encoded data unit can be received from a solid-state memory array. As part of performing the LDPC decoding process, the decoder can (i) convert reliability information representing first non-binary values to reliability information representing first binary values, (ii) determine reliability information representing second binary values using the reliability information representing first binary values, and (iii) convert the reliability information representing the second binary values to reliability information representing second non-binary values.
摘要翻译：在一个实施例中，电子系统包括解码器，其被配置为使用多个可变节点和多个校验节点对编码数据单元进行解码，以执行低密度奇偶校验（LDPC）解码过程。可以从固态存储器阵列接收编码数据单元。作为执行LDPC解码处理的一部分，解码器可以（i）将表示第一非二进制值的可靠性信息转换为表示第一二进制值的可靠性信息，（ii）使用表示第二二进制值的可靠性信息来确定表示第二二进制值的可靠性信息，和（iii）将表示第二二进制值的可靠性信息转换为表示第二非二进制值的可靠性信息。

46. 发明授权

US09391647B2 Decoder and decoding method thereof for min-sum algorithm low density parity-check code 有权
标题翻译：用于最小和算法低密度奇偶校验码的解码器及其解码方法
公开(公告)号：US09391647B2
公开(公告)日：2016-07-12
申请号：US14335392
申请日：2014-07-18
申请人： STORART TECHNOLOGY CO. LTD.
发明人： Jui-Hui Hung , Chih-Nan Yen
IPC分类号： H03M13/00 , H03M13/11 , H03M13/37 , H04L1/00
CPC分类号： H03M13/6566 , H03M13/11 , H03M13/1102 , H03M13/1105 , H03M13/1114 , H03M13/112 , H03M13/1122 , H03M13/1131 , H03M13/114 , H03M13/1162 , H03M13/3746 , H04L1/0061
摘要： The present disclosure illustrates a decoder for min-sum algorithm low density parity-check code. The decoder is adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes a plurality of calculation units, and the memory includes a plurality of memory units. Each calculation unit includes a check node unit, a first message re-constructor and a second message re-constructor. The calculation module divides the coding data into several data groups, and the data group is calculated by each calculation unit. The check node unit generates a stored-form of a calculating result by calculating the respective data group. The calculating result is reconstructed by the first message re-constructor and summed with the following data group. The memory unit stores the respective calculating result generated from the calculation unit.
摘要翻译：本公开示出了用于最小和算法低密度奇偶校验码的解码器。解码器适于对具有位节点和校验节点的编码数据进行解码。解码器包括计算模块和存储器。计算模块包括多个计算单元，并且存储器包括多个存储器单元。每个计算单元包括校验节点单元，第一消息重构器和第二消息重建器。计算模块将编码数据分成若干数据组，并由每个计算单元计算数据组。校验节点单元通过计算各个数据组生成计算结果的存储形式。计算结果由第一个消息重建器重建，并与以下数据组相加。存储单元存储从计算单元生成的相应的计算结果。

47. 发明授权

US09336077B2 Method and apparatus for decoding LDPC code 有权
标题翻译： LDPC码解码方法和装置
公开(公告)号：US09336077B2
公开(公告)日：2016-05-10
申请号：US14031882
申请日：2013-09-19
申请人： Electronics and Telecommunications Research Institute
发明人： Sung Ik Park , Heung Mook Kim
IPC分类号： H03M13/11 , G06F11/10 , H03M13/53
CPC分类号： G06F11/10 , H03M13/112
摘要： There are provided a method and apparatus for decoding an LDPC code. In this specification, a first result is calculated by performing the calculation of a check node having two inputs forward and recursively, a second result is calculated by performing the calculation of the check node having the two inputs backward and recursively, and the check node is calculated using the first result and the second result as the inputs.
摘要翻译：提供了一种用于对LDPC码进行解码的方法和装置。在本说明书中，通过进行具有前向和递归的两个输入的校验节点的计算来计算第一结果，通过反向和递归地执行具有两个输入的校验节点的计算来计算第二结果，并且校验节点使用第一个结果和第二个结果作为输入计算。

48. 发明申请

US20160043744A1 SYSTEMS AND METHODS FOR ADVANCED ITERATIVE DECODING AND CHANNEL ESTIMATION OF CONCATENATED CODING SYSTEMS 审中-公开
公开(公告)号：US20160043744A1
公开(公告)日：2016-02-11
申请号：US14825531
申请日：2015-08-13
申请人： Digital PowerRadio, LLC
发明人： Branimir R. Vojcic , Farnaz Shayegh
IPC分类号： H03M13/29 , H03M13/27
CPC分类号： H04L1/0045 , G06F11/1625 , H03M13/09 , H03M13/1108 , H03M13/1111 , H03M13/112 , H03M13/1131 , H03M13/1154 , H03M13/1191 , H03M13/1515 , H03M13/23 , H03M13/255 , H03M13/27 , H03M13/2792 , H03M13/2906 , H03M13/2933 , H03M13/2948 , H03M13/3707 , H03M13/373 , H03M13/3746 , H03M13/3784 , H03M13/3938 , H03M13/45 , H03M13/451 , H03M13/453 , H03M13/612 , H03M13/616 , H03M13/6325 , H03M13/6337 , H03M13/6362 , H03M13/6541 , H03M13/6552 , H03M13/658 , H04B17/309 , H04L1/004 , H04L1/005 , H04L1/0057 , H04L1/0059 , H04L1/0065 , H04L1/0071 , H04L25/022 , H04L25/0222 , H04L25/0224 , H04L25/0236 , H04L27/261 , H04L27/2649
摘要： Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD Radio signals, including enhanced decoding of reference subcarriers based on soft-diversity combining, joint enhanced channel state information estimation, as well as iterative soft-input soft-output and list decoding of convolutional codes and Reed-Solomon codes. These and other improvements enhance the decoding of different logical channels in HD Radio systems.

49. 发明授权

US09048867B2 Shift register-based layered low density parity check decoder 有权
标题翻译：基于移位寄存器的分层低密度奇偶校验解码器
公开(公告)号：US09048867B2
公开(公告)日：2015-06-02
申请号：US13898685
申请日：2013-05-21
申请人： LSI Corporation
发明人： Dan Liu , Qi Zuo , Chung-Li Wang , Zongwang Li , Lei Wang
IPC分类号： H03M13/11 , H04L1/00
CPC分类号： H03M13/1105 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1122 , H03M13/1131 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1162 , H03M13/1171 , H03M13/1174 , H03M13/6331 , H03M13/6505 , H03M13/658 , H03M13/6583 , H04L1/005
摘要： An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.
摘要翻译：用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

50. 发明授权

US08930790B1 Method and apparatus for identifying selected values from among a set of values 有权
标题翻译：用于从一组值中识别所选值的方法和装置
公开(公告)号：US08930790B1
公开(公告)日：2015-01-06
申请号：US14027081
申请日：2013-09-13
申请人： Antcor S.A.
发明人： Ioannis Tsatsaragkos , Nikolaos L. Kanistras , Vassilis Paliouras
IPC分类号： H03M13/00 , G06F11/07 , H03M13/11
CPC分类号： G06F11/0751 , H03M13/1102 , H03M13/112 , H03M13/1122 , H03M13/6502 , H03M13/6572 , H03M13/658
摘要： The present invention is directed toward identifying selected values from among a set of values. In accordance with an embodiment, a method of identifying two selected values from among a plurality of values comprises: partitioning the plurality of values into pairs of values; for each pair of values, using a comparator to select one of the two values to form a vector from the selected value of each pair; and applying the vector to a hardware unit that identifies first and second extreme values from among the values of the vector.
摘要翻译：本发明旨在从一组值中识别所选择的值。根据实施例，从多个值中识别两个选择的值的方法包括：将所述多个值分成多对值; 对于每对值，使用比较器从两个值的选择值中选择两个值中的一个来形成向量; 以及将所述向量应用于从所述向量的值中识别第一和第二极值的硬件单元。

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