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41. 发明申请

US20110151616A1 MBE GROWTH TECHNIQUE FOR GROUP II-VI INVERTED MULTIJUNCTION SOLAR CELLS 有权
标题翻译：用于组II-VI反相多功能太阳能电池的MBE增长技术
公开(公告)号：US20110151616A1
公开(公告)日：2011-06-23
申请号：US12641049
申请日：2009-12-17
申请人： Sivalingam SIVANANTHAN , James W. GARLAND , Michael W. CARMODY
发明人： Sivalingam SIVANANTHAN , James W. GARLAND , Michael W. CARMODY
IPC分类号： H01L21/10
CPC分类号： H01L31/0296 , H01L21/02381 , H01L21/02395 , H01L21/02469 , H01L21/0248 , H01L21/02485 , H01L31/073 , H01L31/1836 , H01L31/1892 , Y02E10/543 , Y02P70/521
摘要： A method of forming a Group II-VI multijunction semiconductor device comprises providing a Group IV substrate, forming a first subcell from a first Group II-VI semiconductor material, forming a second subcell from a second Group II-VI semiconductor material, and removing the substrate. The first subcell is formed over the substrate and has a first bandgap, while the second subcell is formed over the first subcell and has a second bandgap which is smaller than the first bandgap. Additional subcells may be formed over the second subcell with the bandgap of each subcell smaller than that of the preceding subcell and with each subcell preferably separated from the preceding subcell by a tunnel junction. Prior to the removal of the substrate, a support layer is affixed to the last-formed subcell in opposition to the substrate.
摘要翻译：形成II-VI族多结半导体器件的方法包括提供IV族衬底，从第一组II-VI半导体材料形成第一子电池，从第二组II-VI半导体材料形成第二子电池，基质。第一子电池形成在衬底上并且具有第一带隙，而第二子电池形成在第一子电池上，并且具有小于第一带隙的第二带隙。可以在第二子小区上形成附加的子小区，每个子小区的带隙小于先前的小区的带隙，并且每个子小区优选地通过隧道连接与前一子小区分离。在去除衬底之前，将支撑层固定到与衬底相对的最后形成的子电池上。

42. 发明申请

US20110057295A1 EPITAXIAL SUBSTRATE COMPONENT MADE THEREWITH AND CORRESPONDING PRODUCTION METHOD 审中-公开
标题翻译：外延衬底组件及其相应的生产方法
公开(公告)号：US20110057295A1
公开(公告)日：2011-03-10
申请号：US12940238
申请日：2010-11-05
申请人： Andreas Plossl
发明人： Andreas Plossl
IPC分类号： H01L29/20 , H01L33/00
CPC分类号： C30B29/403 , C30B25/18 , H01L21/02395 , H01L21/02463 , H01L21/02502 , H01L21/02505 , H01L21/02513 , H01L21/02546 , H01L21/76251 , H01L33/0079
摘要： Proposed is a III-V-semiconductor-containing epitaxial substrate comprising at least one layer of porous III-V semiconductor material, together with a corresponding production method. Also specified is a component, particularly an LED, produced on the proposed epitaxial substrate, and a corresponding production method.
摘要翻译：提出的是包含至少一层多孔III-V半导体材料的含III-V族半导体的外延衬底，以及相应的制备方法。还指出了在所提出的外延衬底上制造的部件，特别是LED，以及相应的制造方法。

43. 发明授权

US07893463B2 Integrated devices on a common compound semiconductor III-V wafer 有权
标题翻译：在普通化合物半导体III-V晶片上的集成器件
公开(公告)号：US07893463B2
公开(公告)日：2011-02-22
申请号：US12778307
申请日：2010-05-12
申请人： Paul Cooke , Richard W. Hoffman, Jr. , Victor Labyuk , Sherry Qianwen Ye
发明人： Paul Cooke , Richard W. Hoffman, Jr. , Victor Labyuk , Sherry Qianwen Ye
IPC分类号： H01L29/66
CPC分类号： H01L29/66462 , H01L21/0237 , H01L21/02395 , H01L21/02463 , H01L21/02546 , H01L21/02661 , H01L27/0605 , H01L29/66318 , H01L29/66924
摘要： An integrated pair of HBT and FET transistors shares a common compound semiconductor III-V epitaxial layer. The integrated pair of transistors includes a semi-insulating substrate of a compound semiconductor III-V material, a first epitaxial structure disposed on top of the substrate, a second epitaxial structure on top of the first epitaxial structure, and a third epitaxial structure disposed on top of the second epitaxial structure. The first epitaxial structure forms a portion of the HBT transistor. A concentration profile of a first contaminant, which contributes electrical charge, decreases substantially smoothly across an interface between the semi-insulating substrate and the first epitaxial structure. In some cases, the interface is free of a second contaminant that was present, during formation of the epitaxial structures, in a chamber in which the epitaxial structures were formed.
摘要翻译：一对HBT和FET晶体管共享一个普通的化合物半导体III-V外延层。集成的一对晶体管包括化合物半导体III-V材料的半绝缘衬底，设置在衬底顶部的第一外延结构，在第一外延结构的顶部上的第二外延结构和设置在第一外延结构上的第三外延结构第二外延结构的顶部。第一外延结构形成HBT晶体管的一部分。有助于电荷的第一污染物的浓度分布通过半绝缘衬底和第一外延结构之间的界面基本平滑地减小。在一些情况下，界面在形成外延结构的腔室中没有形成外延结构的第二污染物。

44. 发明申请

US20110003413A1 MANUFACTURING METHOD OF SEMICONDUCTOR PHOTONIC DEVICE SUBSTRATE 有权
标题翻译：半导体光电器件基板的制造方法
公开(公告)号：US20110003413A1
公开(公告)日：2011-01-06
申请号：US12766684
申请日：2010-04-23
申请人： Toshihiro Morisawa , Takehiko Tani , Hisataka Nagai , Takashi Furuya
发明人： Toshihiro Morisawa , Takehiko Tani , Hisataka Nagai , Takashi Furuya
IPC分类号： H01L21/20
CPC分类号： C23C16/56 , H01L21/02395 , H01L21/02543 , H01L33/007 , H01L33/46
摘要： In a manufacturing method of a semiconductor photonic device substrate, before multi-layer films different in material composition are successively and gradually crystal-grown in one chamber, an inter-layer growth rate model showing a relation in growth rate between each layer is defined, a growth rate of a film corresponding to at least one or more layers is obtained by actual crystal growth using an individual substrate, a growth rate of a film corresponding to other layers is estimated from the obtained growth rate by the inter-layer growth rate model, and a growth time is determined in accordance with a film thickness of each layer of the semiconductor photonic device substrate based on the actually obtained growth rate and the estimated growth rate. These steps are carried out by using a computer system connected to an MOCVD equipment, and then, a crystal growth of the semiconductor photonic device substrate is performed.
摘要翻译：在半导体光子器件衬底的制造方法中，在不同材料组成的多层膜在一个室中连续逐渐晶体生长的情况下，定义表示各层之间的生长速度关系的层间生长速率模型，通过使用单个基板的实际晶体生长获得对应于至少一个或多个层的膜的生长速率，通过层间生长速率模型从获得的生长速率估计与其它层相对应的膜的生长速率根据实际获得的生长速度和估计的生长速度，根据半导体光子器件基板的各层的膜厚确定生长时间。这些步骤通过使用连接到MOCVD设备的计算机系统进行，然后执行半导体光子器件衬底的晶体生长。

45. 发明申请

US20100270568A1 Light Emitting Device and Method of Fabricating the Same 有权
标题翻译：发光装置及其制造方法
公开(公告)号：US20100270568A1
公开(公告)日：2010-10-28
申请号：US12303662
申请日：2007-05-29
申请人： Yukari Suzuki , Jun Ikeda , Jun-ya Ishizaki , Shunichi Ikeda
发明人： Yukari Suzuki , Jun Ikeda , Jun-ya Ishizaki , Shunichi Ikeda
IPC分类号： H01L33/02 , H01L33/30
CPC分类号： H01L33/0079 , H01L21/02392 , H01L21/02395 , H01L21/02461 , H01L21/02543 , H01L21/02576 , H01L24/05 , H01L33/02 , H01L33/025 , H01L2224/04042 , H01L2224/48463
摘要： A light emitting device comprises a light emitting layer section having a double heterostructure of an n-type cladding layer, an active layer and a p-type cladding layer, each composed of AlGaInP stacked in this order. Supposing a bonding object layer having a first main surface side as p type and a second main surface side as n type, a light extraction side electrode is formed to cover the first main surface partially. An n-type transparent device substrate composed of Group III-V compound semiconductor having greater band gap energy than the active layer is bonded to the second main surface of the bonding object layer. On one sides of the transparent device substrate and the bonding object layer, a bonding surface to the other is formed, and an InGaP intermediate layer is formed to have a high concentration Si doping layer formed on the bonding surface side.
摘要翻译：发光器件包括具有由依次层叠的AlGaInP构成的n型包覆层，有源层和p型覆层的双异质结构的发光层部。假设具有第一主表面侧为p型，第二主面侧为n型的接合对象层，形成有一部分覆盖第一主面的光提取侧电极。由具有比有源层更大的带隙能量的III-V族化合物半导体构成的n型透明器件基板被接合到接合目标层的第二主表面。在透明器件基板和接合目标层的一侧上，形成彼此的接合表面，并且形成InGaP中间层以在接合表面侧上形成高浓度的Si掺杂层。

46. 发明申请

US20100221512A1 DIGITAL METAMORPHIC ALLOYS FOR GRADED BUFFERS 审中-公开
标题翻译：用于分级缓冲器的数字元素合金
公开(公告)号：US20100221512A1
公开(公告)日：2010-09-02
申请号：US12395564
申请日：2009-02-27
申请人： Kenneth E. Lee , Eugene A. Fitzgerald
发明人： Kenneth E. Lee , Eugene A. Fitzgerald
IPC分类号： B32B7/02 , B05D1/36
CPC分类号： H01L21/02543 , H01L21/02395 , H01L21/02461 , H01L21/02463 , H01L21/02507 , H01L21/0251 , H01L21/0262 , Y10T428/2495
摘要： Digital metamorphic alloy (DMA) buffer structures for transitioning from a bottom crystalline layer to a lattice mismatched top crystalline layer, and methods for manufacturing such layers are described. In some embodiments, a layered crystalline structure includes a first layer of a first crystalline material having a first in-plane lattice constant and a second layer of a second crystalline material disposed over the first layer and having a second in-plane lattice constant that is lattice mismatched with the first crystalline material. Multiple sets of buffer layers may be disposed between the first layer and the second layer. Each set is a digital metamorphic alloy including a buffer layer of a third crystalline material and a buffer layer of a fourth crystalline material where an effective in-plane lattice constant of each set falls between the first lattice of the first layer and the second lattice constant of the second layer.
摘要翻译：描述了从底部结晶层转变为晶格失配顶部晶体层的数字变质合金（DMA）缓冲结构以及制造这种层的方法。在一些实施例中，层状晶体结构包括具有第一面内晶格常数的第一晶体材料的第一层和设置在第一层上并具有第二平面晶格常数的第二晶体材料的第二层，晶格与第一结晶材料不匹配。可以在第一层和第二层之间设置多组缓冲层。每组是包含第三结晶材料的缓冲层和第四晶体材料的缓冲层的数字变质合金，其中每组的有效面内晶格常数落在第一层的第一晶格和第二晶格常数之间的第二层。

47. 发明申请

US20100028605A1 SUBSTRATE FOR EPITAXIAL GROWTH 审中-公开
标题翻译：外源生长基质
公开(公告)号：US20100028605A1
公开(公告)日：2010-02-04
申请号：US12345933
申请日：2008-12-30
申请人： Yuichi OSHIMA
发明人： Yuichi OSHIMA
IPC分类号： B32B3/00
CPC分类号： H01L21/0262 , H01L21/02021 , H01L21/02395 , H01L21/02543 , H01L21/02573 , H01L21/02658 , Y10T428/24479
摘要： A chamfering part is partially formed on the backside, opposite to the front side of a substrate on which epitaxial growth is performed. When a size of the substrate is set at x (mm), preferably length of the chamfering part applied to the backside of the substrate is set at 2 mm or more and 0.15x (mm) or less. In addition, when the substrate is placed on a flat surface, with the front side turned up, preferably height and depth of a gap formed between the substrate and the flat surface are set at 0.2 mm or more.
摘要翻译：倒角部分形成在背面，与进行外延生长的基板的正面相反。当将基板的尺寸设定为x（mm）时，优选施加到基板的背面的倒角部的长度设定为2mm以上且0.15×（mm）以下。此外，当将基板放置在平坦表面上时，正面翻转，优选地将形成在基板和平坦表面之间的间隙的高度和深度设定为0.2mm以上。

48. 发明授权

US07619301B2 GaAs semiconductor substrate and fabrication method thereof 有权
标题翻译： GaAs半导体衬底及其制造方法
公开(公告)号：US07619301B2
公开(公告)日：2009-11-17
申请号：US11907017
申请日：2007-10-09
申请人： Takayuki Nishiura , Yoshio Mezaki , Yusuke Horie , Yasuaki Higuchi
发明人： Takayuki Nishiura , Yoshio Mezaki , Yusuke Horie , Yasuaki Higuchi
IPC分类号： H01L29/201 , C23G1/02
CPC分类号： H01L21/02052 , C30B29/42 , C30B33/10 , H01L21/02008 , H01L21/02395 , H01L21/0254 , H01L21/3245
摘要： A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle θ by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
摘要翻译： GaAs半导体衬底包括表面层。当使用通过X射线光电子能谱测定的光电子取出角θ的10°条件下的Ga原子和As原子的3d电子光谱来计算原子比时，所有Ga原子与表面层的所有As原子（Ga）/（As）为至少0.5且不大于0.9，与O原子键合的所有Ga原子和所有As原子（As-O）/ {（Ga ）+（As）}为0.15以上且0.35以下，与O原子键合的Ga原子与所有Ga原子和所有As原子（Ga-O）/ {（Ga）+（ As）}为0.15以上0.35以下。因此，提供了一种GaAs半导体衬底，其具有通过至少对衬底进行热清洁的方式清洁到允许在表面去除杂质和氧化物的程度的表面。

49. 发明授权

US07608859B2 Semiconductor light-emitting device with transparent conductive film 失效
标题翻译：具有透明导电膜的半导体发光器件
公开(公告)号：US07608859B2
公开(公告)日：2009-10-27
申请号：US11485316
申请日：2006-07-13
申请人： Taichiroo Konno , Kazuyuki Iizuka , Masahiro Arai
发明人： Taichiroo Konno , Kazuyuki Iizuka , Masahiro Arai
IPC分类号： H01L27/15
CPC分类号： H01L33/14 , H01L21/02395 , H01L21/02461 , H01L21/02463 , H01L21/02546 , H01L33/02 , H01L33/025
摘要： A semiconductor light-emitting device with a transparent conductive film has: a light-emitting portion formed on a semiconductor substrate, the light-emitting portion having an n-type clad layer, an active layer and a p-type clad layer; an As-based contact layer formed on the light-emitting portion, the contact layer being doped with a p-type dopant of 1×1019/cm3 or more; a current spreading layer formed on the contact layer, the current spreading layer being formed of a transparent conductive film made of a metal oxide material; and a buffer layer formed between the contact layer and the p-type clad layer. The buffer layer has two or more buffer layer parts, and the adjacent buffer layer parts are different each other in material or composition.
摘要翻译：具有透明导电膜的半导体发光器件具有形成在半导体衬底上的发光部分，所述发光部分具有n型覆盖层，有源层和p型覆盖层; 形成在发光部分上的As基接触层，所述接触层掺杂有1×1019 / cm3以上的p型掺杂剂; 形成在所述接触层上的电流扩展层，所述电流扩散层由由金属氧化物材料制成的透明导电膜形成; 以及形成在所述接触层和所述p型覆盖层之间的缓冲层。缓冲层具有两个以上的缓冲层部分，相邻的缓冲层部分在材料或组成上彼此不同。

50. 发明授权

US07598158B1 Method and device for growing pseudomorphic AlInAsSb on InAs 失效
标题翻译：用于在InAs上生长伪晶AlInAsSb的方法和装置
公开(公告)号：US07598158B1
公开(公告)日：2009-10-06
申请号：US11447338
申请日：2006-06-05
申请人： Peter Deelman , Ken Elliott , David Chow
发明人： Peter Deelman , Ken Elliott , David Chow
IPC分类号： H01L21/20
CPC分类号： H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/02549 , H01L21/02631
摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.
摘要翻译：正在公开半导体器件和方法。半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与彼此由一个III-V组单独的三层组成。该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

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