专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06291836B1 Method of operating a programmable, non-volatile memory device 失效
标题翻译：操作可编程的非易失性存储器件的方法
公开(公告)号：US06291836B1
公开(公告)日：2001-09-18
申请号：US08866649
申请日：1997-05-30
申请人： Niels Kramer , Maarten J. H. Niesten , Wilhelmus H. M. Lodders , Gerrit Oversluizen
发明人： Niels Kramer , Maarten J. H. Niesten , Wilhelmus H. M. Lodders , Gerrit Oversluizen
IPC分类号： H01L218246
CPC分类号： G11C16/02 , G11C17/14 , H01L21/822 , H01L27/10
摘要： The invention relates to an erasable non-volatile memory in which a diode is formed at each point of intersection between the x-selection lines (Ki) and y-selection lines (Rj), of which diode the anode and cathode are conductively connected to the x- and y-selection lines. The diodes are formed in hydrogenated amorphous silicon or silicon compounds such as amorphous Si−xGex. Writing takes place by means of a current pulse through selected diodes. The current in the forward direction becomes much lower, for example a few hundred times lower, than in diodes which are not selected, probably owing to degradation in the semiconductor material. The diodes may be returned to their original state again (i.e. be erased) through heating, for example at a temperature of 200° C. during 100 minutes. Preferably, the diodes are formed by Schottky diodes because the characteristic in the reverse direction does not (substantially) change in this type of diode. The Schottky diodes may be formed in the transitional region between the amorphous intrinsic semiconductor material (6) and the selection lines (Ki).
摘要翻译：本发明涉及一种可擦除非易失性存储器，其中在x选择线（Ki）和y选择线（Rj）之间的每个交点处形成二极管，其中阳极和阴极二极管导电连接到 x和y选择行。二极管形成在氢化非晶硅或硅化合物如非晶Si-xGex中。通过选定二极管的电流脉冲进行写入。正向方向上的电流比未选择的二极管低得多，例如低几百倍，可能是由于半导体材料的劣化。二极管可以通过加热再次（即被擦除）返回到其原始状态，例如在200℃的温度下在100分钟内。优选地，二极管由肖特基二极管形成，因为在这种类型的二极管中反向特性不会（基本上）改变。肖特基二极管可以形成在非晶本征半导体材料（6）和选择线（Ki）之间的过渡区域中。

42. 发明申请

US20010010649A1 Novel flash memory using micro vacuum tube technology 有权
标题翻译：新型闪存采用微型真空管技术
公开(公告)号：US20010010649A1
公开(公告)日：2001-08-02
申请号：US09784820
申请日：2001-02-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
发明人： Nai-Cheng Lu
IPC分类号： G11C011/34
CPC分类号： H01L29/7881 , G11C16/02 , G11C16/0416 , H01J19/24 , H01J21/105
摘要： In this invention a micro vacuum tube is used to form a flash memory cell. The micro vacuum tube is position over a floating gate and is used to program, erase, read and deselect the flash memory cell. A first embodiment includes a source and drain with the floating gate to provide a means to produce bit line current to be read by the flash memory sense amplifiers. In a second embodiment the source and drain are eliminated and cathode gate current is used to indicate the state of the flash memory cell. In a third embodiment the floating gate is replace with a diffusion in the semiconductor substrate. The cathode tip is formed by filling a depression in a sacrificial material used to temporarily fill the volume that will be the vacuum chamber when the vacuum tube is completed. The tip can be a convex cusp producing a needle like point or an elongated convex cusp having an sharp line edge. The two different shaped cathode tips depend on the shape of the vacuum chamber, and the elongated convex cusp produces a more efficient emission of electron.
摘要翻译：在本发明中，使用微型真空管来形成闪存单元。微型真空管位于浮动栅极上，用于对闪存单元进行编程，擦除，读取和取消选择。第一实施例包括具有浮动栅极的源极和漏极，以提供产生要由闪存读出放大器读取的位线电流的装置。在第二实施例中，消除了源极和漏极，并且使用阴极栅极电流来指示闪存单元的状态。在第三实施例中，浮置栅极被替换为半导体衬底中的扩散。当真空管完成时，通过在牺牲材料中填充用于临时填充真空室的体积的牺牲材料来形成阴极尖端。尖端可以是产生针状点的凸起尖点或具有尖锐线边缘的细长凸起尖点。两个不同形状的阴极尖端取决于真空室的形状，并且细长凸起尖端产生更有效的电子发射。

43. 发明授权

US06243282B1 Apparatus for on-board programming of serial EEPROMs 有权
标题翻译：用于串行EEPROM的板上编程的装置
公开(公告)号：US06243282B1
公开(公告)日：2001-06-05
申请号：US09659471
申请日：2000-09-11
申请人： Thomas C. Rondeau, II , Allan R. Magee
发明人： Thomas C. Rondeau, II , Allan R. Magee
IPC分类号： G11C502
CPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , G11C11/005 , G11C16/02 , G11C16/102 , G11C16/20 , G11C2029/4402 , H05K1/0266 , H05K1/029 , H05K1/18 , H05K2201/10022
摘要： A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after complet assembly of the memory module. The memory module includes a plurality of edge connectors for electrically connecting the memory module circuitry external to the memory module, and a plurality of DRAM memory devices electrically connected to corresponding edge connectors for receiving and providing data from and to the external circuitry. The memory module also includes a Serial EEPROM for storing the module information. The Serial EEPROM has a Serial Data pin connected to a first of the edge connectors for providing the module information to the external circuitry. The Serial EEPROM has a Write Control pin for receiving an enabling signal which selectively enables the operation of the Serial EEPROM in Write or Read-Only mode. The memory module further includes interface circuitry which couples the Write Control pin with a second and a third of the edge connectors. The Write Control pin is coupled to the second edge connector, where VSS is applied, by circuit element, such as a jumper, suitable for temporarily connecting the Write Control pin to the second edge connector. A resistor couples the Write Control pin to the third edge connector where VCC is applied.
摘要翻译：描述了一种存储器模块，其可以在完成组装存储器模块之后用模块信息进行编程，以识别存储器模块的类型和尺寸。存储器模块包括用于电连接存储器模块外部的存储器模块电路的多个边缘连接器以及电连接到相应的边缘连接器的多个DRAM存储器件，用于从外部电路接收和提供数据。存储器模块还包括用于存储模块信息的串行EEPROM。串行EEPROM具有连接到第一个边缘连接器的串行数据引脚，用于将模块信息提供给外部电路。串行EEPROM具有写控制引脚，用于接收使能信号，选择性地使能串行EEPROM的写操作或只读模式。存储器模块还包括将写控制引脚与第二和第三边缘连接器耦合的接口电路。写控制引脚通过诸如跳线的电路元件耦合到施加VSS的第二边缘连接器，适于临时将写控制引脚连接到第二边缘连接器。一个电阻将写控制引脚耦合到施加VCC的第三个边沿连接器。

44. 发明授权

US4879256A Method of controlling the order-disorder state in a semiconductor device 失效
标题翻译：控制半导体器件中的无序状态的方法
公开(公告)号：US4879256A
公开(公告)日：1989-11-07
申请号：US331063
申请日：1989-03-28
申请人： John C. Bean , Abbas Ourmazd
发明人： John C. Bean , Abbas Ourmazd
IPC分类号： G11C16/02 , H01L27/146 , H01L29/15 , H01L29/80
CPC分类号： G11C16/02 , H01L27/14643 , H01L29/155 , H01L29/802
摘要： An ordered-disordered transition is observed in semiconductor alloys which enables either the ordered or disordered structure to be produced.
摘要翻译：在半导体合金中观察到有序无序的转变，这使得可以产生有序或无序结构。

45. 发明公开

US20240379837A1 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATH 审中-公开
公开(公告)号：US20240379837A1
公开(公告)日：2024-11-14
申请号：US18778978
申请日：2024-07-20
申请人： Monolithic 3D Inc.
发明人： Zvi Or-Bach
IPC分类号： H01L29/78 , G11C11/404 , G11C11/4097 , G11C11/412 , G11C16/02 , G11C16/04 , H10B10/00 , H10B12/00 , H10B43/20 , H10B63/00 , H10B69/00
CPC分类号： H01L29/78 , G11C11/404 , G11C11/4097 , G11C16/02 , H01L29/7841 , H10B10/12 , H10B12/20 , H10B43/20 , H10B63/30 , H10B69/00 , G11C11/412 , G11C16/0483 , G11C2213/71
摘要： A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the plurality of capacitors include functioning as a decoupling capacitor to mitigate power supply noise.

46. 发明授权

US11869965B2 3D semiconductor device and structure with metal layers and memory cells 有权
公开(公告)号：US11869965B2
公开(公告)日：2024-01-09
申请号：US18227183
申请日：2023-07-27
申请人： Monolithic 3D Inc.
发明人： Zvi Or-Bach
IPC分类号： H01L29/78 , G11C16/02 , G11C11/404 , G11C11/4097 , H10B10/00 , H10B12/00 , H10B43/20 , H10B69/00 , H10B63/00 , G11C11/412 , G11C16/04
CPC分类号： H01L29/78 , G11C11/404 , G11C11/4097 , G11C16/02 , H01L29/7841 , H10B10/12 , H10B12/20 , H10B43/20 , H10B63/30 , H10B69/00 , G11C11/412 , G11C16/0483 , G11C2213/71
摘要： A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.

47. 发明公开

US20230155018A1 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY 审中-公开
公开(公告)号：US20230155018A1
公开(公告)日：2023-05-18
申请号：US18092727
申请日：2023-01-03
申请人： Monolithic 3D Inc.
发明人： Zvi Or-Bach
IPC分类号： H01L29/78 , G11C16/02 , G11C11/404 , G11C11/4097 , H10B10/00 , H10B12/00 , H10B43/20 , H10B69/00 , H10B63/00
CPC分类号： H01L29/78 , G11C16/02 , G11C11/404 , G11C11/4097 , H01L29/7841 , H10B10/12 , H10B12/20 , H10B43/20 , H10B69/00 , H10B63/30 , G11C11/412
摘要： A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.

48. 发明授权

US10839917B2 Memory device 有权
公开(公告)号：US10839917B2
公开(公告)日：2020-11-17
申请号：US16352094
申请日：2019-03-13
申请人： Toshiba Memory Corporation
发明人： Tomoko Araya , Mitsuaki Honma
IPC分类号： G11C16/26 , G11C16/04 , G11C29/52 , G06F11/10 , G11C11/56 , G11C16/02 , G11C16/06
CPC分类号： G11C16/26 , G06F11/1048 , G06F11/1068 , G11C11/5642 , G11C16/02 , G11C16/0483 , G11C16/06 , G11C29/52
摘要： According to one embodiment, a memory device, includes a first memory cell, and a second memory cell adjacent to the first memory cell; and a sequencer configured to, when data is read from the first memory cell: perform a first read operation on the second memory cell; perform a second read operation on the first memory cell; perform a third read operation on the first memory cell by applying a voltage different from that applied in the second read operation to a gate of the second memory cell; and generate first data stored in the first memory cell and second data for correcting the first data, based on results of the first to third read operations.

49. 发明申请

US20190243405A1 CURRENT SOURCE 审中-公开
公开(公告)号：US20190243405A1
公开(公告)日：2019-08-08
申请号：US16342997
申请日：2017-10-03
申请人： ASAHI KASEI MICRODEVICES CORPORATION
发明人： Toshiro SAKAMOTO , Yuukou TSUSHIMA
IPC分类号： G05F3/24 , G11C16/30 , H01L27/11521 , H01L29/788 , H01L29/792
CPC分类号： G05F3/245 , G05F3/24 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/30 , H01L27/10 , H01L27/115 , H01L27/11521 , H01L29/788 , H01L29/792
摘要： The object of the present invention is to provide a current source which is capable of suppressing an increase in circuit size and by which a highly accurate constant current extremely stable to manufacturing variations or temperature fluctuations can be obtained. A current source circuit is provided with a nonvolatile storage element having a control gate region and a source region and operating as a field-effect transistor, and is configured to output a current in a state where a bias is applied between the control gate region and the source region.

50. 发明申请

US20190042962A1 JOSEPHSON JUNCTIONS FOR IMPROVED QUBITS 审中-公开
公开(公告)号：US20190042962A1
公开(公告)日：2019-02-07
申请号：US15669139
申请日：2017-08-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： David W. Abraham , Josephine B. Chang , Jay M. Gambetta
IPC分类号： G06N99/00 , G11C11/44 , H03K19/195 , H01L27/18 , G11C16/02
CPC分类号： G06N10/00 , G11C11/44 , G11C16/02 , H01L27/18 , H01L39/025 , H01L39/045 , H01L39/22 , H01L39/223 , H01L39/2493 , H03K19/1952
摘要： A technique relates to a superconducting qubit. A Josephson junction includes a first superconductor and a second superconductor formed on a non-superconducting metal. A capacitor is coupled in parallel with the Josephson junction.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式