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41. 发明公开

US20240029987A1 Method, System, and Apparatus to Prevent Electrical or Thermal-Based Hazards in Conduits 审中-公开
公开(公告)号：US20240029987A1
公开(公告)日：2024-01-25
申请号：US18480374
申请日：2023-10-03
申请人： Kenneth G. Blemel , Kenneth D. Blemel , Benjamin Allen Bone , Jesse Min-Tze Adamczyk , Lara Rose Draelos , Mariana Flores-Olivas
发明人： Kenneth G. Blemel , Kenneth D. Blemel , Benjamin Allen Bone , Jesse Min-Tze Adamczyk , Lara Rose Draelos , Mariana Flores-Olivas
IPC分类号： H01H71/10 , H01H71/02 , H01H71/14 , H01H37/74 , G02F1/1333 , G02F1/1362 , G02F1/1368 , G09G3/3266 , G09G3/36 , G11C19/28 , H01L27/105 , H01L27/12 , H01L29/786
CPC分类号： H01H71/10 , H01H71/02 , H01H71/14 , H01H37/74 , G02F1/133345 , G02F1/136286 , G02F1/1368 , G09G3/3266 , G09G3/3677 , G11C19/28 , H01L27/105 , H01L27/12 , H01L27/1214 , H01L27/1222 , H01L27/124 , H01L27/1251 , H01L27/1255 , H01L29/78663 , H01L29/78678 , H01H2071/147 , G02F1/134309
摘要： A method, apparatus, and system for protection from hazards of conductivity is disclosed using non-electrical means to disrupt electrical current with a thermovolumetric substance. The purpose of this invention is to prevent hazardous conditions from occurring by disrupting the flow of electrical current prior to the development of arc fault conditions.

42. 发明授权

US11881188B2 Array substrate including stages of gate array units having different sized output transistors, and display panel 有权
公开(公告)号：US11881188B2
公开(公告)日：2024-01-23
申请号：US16969567
申请日：2020-06-02
申请人： Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
发明人： Zhida Xu , Ilgon Kim
IPC分类号： G09G3/36 , G09G3/3266
CPC分类号： G09G3/3677 , G09G3/3266
摘要： A array substrate includes a plurality of stages of cascaded GOA units and a plurality of corresponding clock signal lines electrically connected to them. Each stage of GOA units includes a first output transistor. In the plurality of stages of GOA units, the plurality of first output transistors increase in size along a predetermined direction. The predetermined direction is a signal transmission direction of any of the clock signal lines.

43. 发明授权

US11869453B2 Display device comprising semiconductor layer having LDD regions 有权
公开(公告)号：US11869453B2
公开(公告)日：2024-01-09
申请号：US17702073
申请日：2022-03-23
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hiroyuki Miyake , Kouhei Toyotaka , Shunpei Yamazaki
IPC分类号： G09G3/36 , G02F1/1333 , G02F1/1345 , G02F1/1368 , G02F1/1343 , G11C19/28 , H01L27/12
CPC分类号： G09G3/3677 , G02F1/1333 , G02F1/1368 , G02F1/13439 , G02F1/13454 , G11C19/28 , H01L27/124 , H01L27/1222 , G02F1/13685 , G09G2300/0809 , G09G2310/0286 , G09G2310/0291
摘要： To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n−3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.

44. 发明授权

US11852924B2 Active matrix substrate and a liquid crystal display 有权
公开(公告)号：US11852924B2
公开(公告)日：2023-12-26
申请号：US18108705
申请日：2023-02-13
申请人： Sharp Kabushiki Kaisha
发明人： Takahiro Mori
IPC分类号： G02F1/1339 , G02F1/1345 , G11C19/28 , G02F1/1335 , G02F1/1368 , G09G3/36 , G02F1/1333 , G02F1/1362
CPC分类号： G02F1/1339 , G02F1/1345 , G02F1/1368 , G02F1/133345 , G02F1/133512 , G02F1/136213 , G09G3/3677 , G11C19/28 , G11C19/287 , G09G2300/0408 , G09G2310/0286
摘要： The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

45. 发明授权

US11847988B2 Driving method for flicker suppression of display panel and driving circuit thereof 有权
公开(公告)号：US11847988B2
公开(公告)日：2023-12-19
申请号：US16983262
申请日：2020-08-03
申请人： SITRONIX TECHNOLOGY CORP.
发明人： Hung-Yu Lu , Rong-Fong Chen
IPC分类号： G09G3/36
CPC分类号： G09G3/3607 , G09G3/3655 , G09G3/3677 , G09G3/3685 , G09G3/3614 , G09G2310/027 , G09G2320/0247 , G09G2320/0276 , G09G2320/0673
摘要： The present invention relates to a driving method for flicker suppression of a display panel and a driving circuit thereof. The driving circuit includes a source driving circuit and a common voltage generating circuit. The driving method includes driving the source driving circuit to generate at least one first source signal and at least one second source signal, the first source signal corresponds to at least one first pixel on a first scanning line; the second source signal corresponds to at least one second pixel on a second scanning line. The common voltage generating circuit generates at least one common voltage. While driving the first pixel and the second pixel to display the same gray scale image, the first source signal is not equal to the second source signal, or a first common voltage and a second common voltage generated by the common voltage generating circuit are different.

46. 发明公开

US20230402019A1 GATE DRIVING CIRCUIT AND DISPLAY PANEL 审中-公开
公开(公告)号：US20230402019A1
公开(公告)日：2023-12-14
申请号：US17419876
申请日：2021-05-31
申请人： WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Yanqing Guan , Chao Tian , Haiming Cao
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2300/0876
摘要： A display panel and a gate driving circuit are provided. The gate driving circuit utilizes the pull-down control module to periodically pull up and pull down the voltage level of the second node. The voltage level of the second node is periodically a high voltage level. This effectively reduces the time duration when the second node corresponds to the high voltage level. After the TFTs electrically connected to the second node are forward biased, the TFTs could have sufficient recovery time. This solution effectively improves the bias condition of the TFTs in the pull-down control module and thus makes the circuit more stable and raises the reliability of the circuit.

47. 发明授权

US11842691B2 Display device including distributed drivers 有权
公开(公告)号：US11842691B2
公开(公告)日：2023-12-12
申请号：US18083646
申请日：2022-12-19
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Yong Sung Park , Dae Hyun Noh
IPC分类号： G09G5/00 , G09G3/3266 , G09G3/3233 , G09G3/3275 , G09G3/32 , G09G3/3241 , G09G3/36
CPC分类号： G09G3/3266 , G09G3/32 , G09G3/3233 , G09G3/3241 , G09G3/3275 , G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2300/0439 , G09G2300/0809 , G09G2300/0819 , G09G2300/0861 , G09G2310/0202 , G09G2310/0216 , G09G2310/0218 , G09G2310/0251 , G09G2310/0262 , G09G2310/0286 , G09G2310/08 , G09G2320/0223 , G09G2320/045 , G09G2340/0435
摘要： A display device including: first pixels connected to a first write line and a first compensation line; second pixels connected to a second write fine and a second compensation line; third pixels connected to a third write line and a third compensation line; fourth pixels connected to a fourth write line and a fourth compensation line; fifth pixels connected to a fifth write line and a fifth compensation line; sixth pixels connected to a sixth write line and a sixth compensation line; seventh pixels connected to a seventh write line and a seventh compensation line; and eighth pixels connected to an eighth write line and an eighth compensation line, the first to fourth compensation lines are connected to a first node, the fifth and sixth compensation lines are connected to a second node, the seventh and eighth compensation lines are connected to a third node.

48. 发明公开

US20230395036A1 DISPLAY APPARATUS AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20230395036A1
公开(公告)日：2023-12-07
申请号：US18235498
申请日：2023-08-18
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kazunori WATANABE , Koji KUSUNOKI
IPC分类号： G09G3/36 , G02F1/1362 , G02F1/1368 , G11C19/28
CPC分类号： G09G3/3677 , G02F1/136286 , G02F1/1368 , G11C19/28 , G09G3/3611 , G09G2310/0267 , G09G2310/0286
摘要： A display apparatus with low power consumption is provided. The display apparatus includes a circuit for boosting a signal voltage output from a gate driver. The signal voltage from the gate driver can be boosted and then supplied to a pixel, which is suitable for driving a display device with a high threshold voltage. Furthermore, by utilizing a boosting function, output of the gate driver can be reduced, and power consumption can also be reduced. By combination with a pixel having a boosting function of image data, a display apparatus with lower power consumption can be achieved.

49. 发明公开

US20230395034A1 Liquid Crystal Display Device And Electronic Device Including The Same 审中-公开
公开(公告)号：US20230395034A1
公开(公告)日：2023-12-07
申请号：US18234752
申请日：2023-08-16
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Atsushi Umezaki
IPC分类号： G09G3/36 , H01L23/528 , G02F1/1345 , G02F1/1362 , H01L29/786 , G11C19/28
CPC分类号： G09G3/3674 , H01L23/528 , G02F1/13454 , G02F1/136286 , G09G3/3677 , H01L29/786 , G11C19/28 , G02F2201/124 , H01L27/1214
摘要： A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

50. 发明授权

US11830454B2 Active matrix substrate and display device 有权
公开(公告)号：US11830454B2
公开(公告)日：2023-11-28
申请号：US18101270
申请日：2023-01-25
申请人： Sharp Display Technology Corporation
发明人： Kengo Hara , Tohru Daitoh , Yoshihito Hara , Jun Nishimura , Yohei Takeuchi
IPC分类号： G09G3/36 , H01L27/12
CPC分类号： G09G3/3677 , H01L27/124 , H01L27/1225 , G09G2310/0286 , G09G2330/021
摘要： An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal. The semiconductor layer includes a source contact region electrically connected to the first source terminal, a drain contact region electrically connected to the first drain terminal, and a first and a second channel regions separated from each other in a channel length direction between the contact regions when viewed from a normal direction of the substrate. The first gate electrode overlaps the first channel region via an upper gate insulating layer, and the second gate electrode overlaps the second channel region via the upper gate insulating layer.

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