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41. 发明授权

US09727465B2 Self-disabling working set cache 有权
公开(公告)号：US09727465B2
公开(公告)日：2017-08-08
申请号：US14253856
申请日：2014-04-15
申请人： Microsoft Technology Licensing, LLC
发明人： David J. Hiniker-Roosa
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0864
CPC分类号： G06F12/0831 , G06F12/0864
摘要： A method to monitor the behavior of a working set cache of a full data set at run time and determine whether it provides a performance benefit is disclosed. An effectiveness metric of the working set cache is tracked over a period of time by efficiently computing the amount of physical memory consumption the cache saves and comparing this to a straightforward measure of its overhead. If the effectiveness metric is determined to be on an ineffective side of a selected threshold amount, the working set cache is disabled. The working set cache can be re-enabled in response to a predetermined event.

42. 发明申请

US20170192893A1 INSTRUCTION TO CANCEL OUTSTANDING CACHE PREFETCHES 审中-公开
公开(公告)号：US20170192893A1
公开(公告)日：2017-07-06
申请号：US15387956
申请日：2016-12-22
申请人： International Business Machines Corporation
发明人： Michael Karl Gschwind , Maged M. Michael , Valentina Salapura , Eric M. Schwarz , Chung-Lung K. Shum
IPC分类号： G06F12/0862 , G06F12/084
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/30087 , G06F9/3802 , G06F9/3814 , G06F9/383 , G06F9/3834 , G06F9/467 , G06F12/0811 , G06F12/0831 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2212/1021 , G06F2212/314 , G06F2212/502 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6026
摘要： Techniques relate to handling outstanding cache miss prefetches. A processor pipeline recognizes that a prefetch canceling instruction is being executed. In response to recognizing that the prefetch canceling instruction is being executed, all outstanding prefetches are evaluated according to a criterion as set forth by the prefetch canceling instruction in order to select qualified prefetches. In response to evaluating, a cache subsystem is communicated with to cause canceling of the qualified prefetches that fit the criterion. In response to successful canceling of the qualified prefetches, a local cache is prevented from being updated from the qualified prefetches.

43. 发明申请

US20170185516A1 SNOOP OPTIMIZATION FOR MULTI-PORTED NODES OF A DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：US20170185516A1
公开(公告)日：2017-06-29
申请号：US14980144
申请日：2015-12-28
申请人： ARM Limited
发明人： Ashley Miles STEVENS , Andrew David TUNE , Daniel Adam SARA
IPC分类号： G06F12/08 , G06F9/30 , G06F15/80 , G06F15/78
CPC分类号： G06F12/0831 , G06F2212/1048
摘要： A data processing apparatus having an interconnect circuit operable to transfer snoop messages between a plurality of connected devices, at least one of which has multiple ports each coupled to a local cache. The interconnect circuit has decode logic that identifies, from an address in a snoop message, which port is coupled to the local cache associated with the address, and the interconnect circuit transmits the snoop message to that port. The interconnect circuit may also have a snoop filter that stores a snoop vector for each block of data in the local caches. Each snoop vector has an address tag that identifies the block of data and a presence vector indicative of which devices of the connected devices have a copy of the block of data. The presence vector does not identify which port of a device has access to the copy.

44. 发明授权

US09690737B2 Systems and methods for controlling access to a shared data structure with reader-writer locks using multiple sub-locks 有权
公开(公告)号：US09690737B2
公开(公告)日：2017-06-27
申请号：US14417233
申请日：2012-07-31
申请人： Joseph A. Tucek
发明人： Joseph A. Tucek
IPC分类号： G06F13/40 , G06F9/52 , G06F12/08 , G06F17/30 , G06F12/0831
CPC分类号： G06F13/4027 , G06F9/526 , G06F12/0831 , G06F17/30132 , G06F17/30171 , G06F2209/523 , G06F2212/621
摘要： A computer system for controlling access to a shared data structure includes a shared memory coupled to first and second processing units that stores a multi-lock to control access to a shared data structure. The multi-lock includes a first sub-lock associated with the first processing unit and a second sub-lock associated with the second processing unit The system also includes a data access control engine to receive a request to read from the data structure from the first processing unit and, as a result, determine whether a privately modifiable copy the first sub-lock exists in a first cache dedicated to the first processing unit, acquire a read portion of the first sub-lock and not communicate the acquisition across a coherence bus if a privately modifiable copy of the first sub-lock exists in the first cache, and if a privately modifiable copy of the first sub-lock does not exist in the first cache, load the first sub-lock into the first cache if no copy is in the first cache, shootdown other copies of the first sub-lock, and acquire the read portion of the first sub-lock.

45. 发明授权

US09684595B2 Adaptive hierarchical cache policy in a microprocessor 有权
公开(公告)号：US09684595B2
公开(公告)日：2017-06-20
申请号：US15162707
申请日：2016-05-24
申请人： Intel Corporation
发明人： Larisa Novakovsky , Joseph Nuzman , Alexander Gendler
IPC分类号： G06F12/0871 , G06F12/0897 , G06F12/0811 , G06F12/0891 , G06F12/0804 , G06F12/0837 , G06F12/0831
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0831 , G06F12/0837 , G06F12/0891 , G06F2212/283 , G06F2212/621
摘要： A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

46. 发明授权

US09652404B2 Multicore, multibank, fully concurrent coherence controller 有权
公开(公告)号：US09652404B2
公开(公告)日：2017-05-16
申请号：US15047318
申请日：2016-02-18
申请人： Texas Instruments Incorporated
发明人： Matthew D. Pierson , Kai Chirca
IPC分类号： G06F12/00 , G06F12/1081 , G06F12/0815 , G06F12/0831 , G06F13/16 , H04L29/06 , G06F13/42 , G06F12/0817 , G06F13/28 , G06F13/40 , G06F12/0842 , G06F13/00
CPC分类号： G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.

47. 发明授权

US09652385B1 Apparatus and method for handling atomic update operations 有权
公开(公告)号：US09652385B1
公开(公告)日：2017-05-16
申请号：US14953093
申请日：2015-11-27
申请人： ARM Limited
发明人： Gregory Andrew Chadwick , Adnan Khan
IPC分类号： G06F12/08 , G06F9/52 , G06F9/38 , G06F12/0802 , G06F12/0815
CPC分类号： G06F9/528 , G06F9/3834 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/1054 , G06F2212/1024 , G06F2212/1032
摘要： An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines. Atomic update handling circuitry is used to handle performance of an atomic update operation in respect of data at a specified address. When data at the specified address is determined to be stored within a cache line of the cache storage, the atomic update handling circuitry performs the atomic update operation on the data from that cache line. Hazard detection circuitry is used to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address. The linefill operation causes the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line. Partial linefill notification circuitry is used to provide partial linefill information to the atomic update handling circuitry during the linefill operation, and the atomic update handling circuitry is arranged to initiate the atomic update operation responsive to detecting from the partial linefill information that the data at the specified address is available for the chosen cache line. This can provide a performance benefit, by avoiding the need for the atomic update handling circuitry to await completion of the linefill operation before beginning the atomic update operation.

48. 发明授权

US09632955B2 Reorder buffer permitting parallel processing operations with repair on ordering hazard detection within interconnect circuitry 有权
公开(公告)号：US09632955B2
公开(公告)日：2017-04-25
申请号：US14628335
申请日：2015-02-23
申请人： ARM LIMITED
发明人： Arthur Laughton , Andrew David Tune , Daniel Sara
IPC分类号： G06F13/16 , G06F12/08 , G06F12/0831
CPC分类号： G06F13/1626 , G06F12/0831 , G06F13/1642 , G06F2212/621
摘要： A system-on-chip integrated circuit 2 includes interconnect circuitry 4 for communicating transactions between transaction sources and transaction destinations. A reorder buffer 26 serves to buffer and permit reordering of access transactions received from the transaction sources. Processing circuitry performs processing operations in parallel upon a given access transaction taken from the reorder buffer. Hazard detection and repair circuitry serves to detect an ordering hazard arising between the processing operations and if necessary cancel and repeat that processing operation. The access transactions and the reorder buffer are such that access transactions other than the access transaction for which a hazard has been detected may proceed independently of the necessity to cancel and repair that transaction thereby reducing the cost associated with cancelling and repair.

49. 发明申请

US20170097907A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 审中-公开
公开(公告)号：US20170097907A1
公开(公告)日：2017-04-06
申请号：US15237291
申请日：2016-08-15
申请人： Intel Corporation
发明人： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Ashish Gupta
IPC分类号： G06F13/22 , G06F13/40 , G06F1/32 , G06F13/42
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.

50. 发明申请

US20170091101A1 Snoop Mechanism And Snoop Filter Structure For Multi-Port Processors 审中-公开
公开(公告)号：US20170091101A1
公开(公告)日：2017-03-30
申请号：US15373038
申请日：2016-12-08
申请人： MediaTek Inc.
发明人： Chien-Hung Lin , Tung-Yao Lee
IPC分类号： G06F12/0831
CPC分类号： G06F12/0831 , G06F2212/1016 , G06F2212/621 , Y02D10/13
摘要： Techniques and examples pertaining to memory coherence management with a snoop mechanism and snoop filter structure for multi-port processors are described. A method may involve receiving a request from a first processor having a first plurality of local memories and more than one snoop ports. Responsive to the request, the method may involve snooping one or more snoop ports of a second processor having a second plurality of local memories without snooping any of the more than one snoop ports of the first processor.

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