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41. 发明申请

US20130307147A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：芯片包装及其形成方法
公开(公告)号：US20130307147A1
公开(公告)日：2013-11-21
申请号：US13895235
申请日：2013-05-15
申请人： XINTEC INC.
发明人： Chien-Hung LIU
IPC分类号： H01L23/498 , H01L21/78
CPC分类号： H01L23/49811 , B81B7/0061 , B81B7/0067 , H01L21/561 , H01L21/76898 , H01L21/78 , H01L23/3114 , H01L23/3128 , H01L27/14618 , H01L33/486 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a chip package including: a substrate having a first surface and a second surface; a device region located in the substrate; a conducting pad structure disposed on the substrate and electrically connected to the device region; a spacer layer disposed on the first surface of the substrate; a second substrate disposed on the spacer layer, wherein a cavity is created and surrounded by the second substrate, the spacer layer, and the substrate on the device region; and a through-hole extending from a surface of the second substrate towards the substrate, wherein the through-hole connects to the cavity.
摘要翻译：本发明的实施例提供一种芯片封装，包括：具有第一表面和第二表面的基板; 位于所述基板中的器件区域; 导电焊盘结构，设置在所述基板上并电连接到所述器件区域; 设置在所述基板的第一表面上的间隔层; 设置在所述间隔层上的第二衬底，其中由所述第二衬底，所述间隔层和所述器件区域上的衬底产生并包围空腔; 以及从所述第二基板的表面朝向所述基板延伸的通孔，其中所述通孔连接到所述空腔。

42. 发明申请

US20130207240A1 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：芯片包装结构及其制造方法
公开(公告)号：US20130207240A1
公开(公告)日：2013-08-15
申请号：US13829802
申请日：2013-03-14
申请人： XINTEC INC.
发明人： Hung-Jen LEE , Shu-Ming CHANG , Chen-Han CHIANG , Tsang-Yu LIU , Yen-Shih HO
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/561 , H01L21/6836 , H01L23/16 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L24/13 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/94 , H01L2221/68327 , H01L2221/68377 , H01L2223/5446 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/131 , H01L2224/29011 , H01L2224/29013 , H01L2224/29124 , H01L2224/2957 , H01L2224/296 , H01L2224/3003 , H01L2224/30155 , H01L2224/32225 , H01L2224/73253 , H01L2224/83125 , H01L2224/83127 , H01L2224/83192 , H01L2224/83895 , H01L2224/94 , H01L2924/014 , H01L2924/12041 , H01L2924/1461 , H01L2224/11 , H01L2224/03 , H01L2224/83 , H01L2924/00014 , H01L2924/01032 , H01L2924/00
摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.
摘要翻译：本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。本发明的另一个实施例提供一种芯片封装结构。

43. 发明申请

US20130154077A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
标题翻译：芯片包装及其形成方法
公开(公告)号：US20130154077A1
公开(公告)日：2013-06-20
申请号：US13720649
申请日：2012-12-19
申请人： Xintec Inc.
发明人： Kuo-Hua LIU , Yi-Ming CHANG , Hsi-Chien LIN
IPC分类号： H01L21/78 , H01L23/48
CPC分类号： H01L21/78 , H01L21/50 , H01L21/561 , H01L23/10 , H01L23/48 , H01L27/14618 , H01L27/14632 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.
摘要翻译：芯片封装包括：具有第一和第二表面的衬底; 形成在基板上或设置在基板上的器件区域; 设置在所述第一表面上的电介质层; 至少一个导电焊盘，其布置在所述电介质层中并电连接到所述器件区域; 设置在所述电介质层上的平面层，其中所述平面层的上表面与所述导电焊盘之间的垂直距离大于约2μm; 设置在所述第一表面上的透明基板; 设置在所述透明基板和所述平面层之间的第一间隔层; 以及第二间隔层，其设置在所述透明基板和所述基板之间并且延伸到所述电介质层的与所述导电焊盘接触的开口中，其中所述第二间隔层和所述导电焊盘之间基本上没有间隙。

44. 发明申请

US20120125668A1 WIRING STRUCTURE FOR IMPROVING CROWN-LIKE DEFECT AND FABRICATION METHOD THEREOF 有权
标题翻译：改善类似缺陷的布线结构及其制造方法
公开(公告)号：US20120125668A1
公开(公告)日：2012-05-24
申请号：US13300392
申请日：2011-11-18
申请人： Yi-Ming CHANG , I-Min Lin , Po-Shen Lin
发明人： Yi-Ming CHANG , I-Min Lin , Po-Shen Lin
IPC分类号： H05K1/09 , H05K3/06
CPC分类号： H05K3/06 , H01L21/4853 , H01L21/7685 , H01L21/76852 , H01L21/76885 , H01L23/53238 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02313 , H01L2224/02317 , H01L2224/02319 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/0401 , H01L2224/05548 , H01L2224/1148 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2924/01029 , H01L2924/12041 , H01L2924/14 , H05K3/244 , H05K3/4007 , H05K2201/0367 , H01L2924/01082 , H01L2924/01047 , H01L2924/00014 , H01L2924/01028 , H01L2924/01079 , H01L2924/00
摘要： A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.
摘要翻译：提供了一种用于改善冠状缺陷的布线结构及其制造方法。该方法包括以下步骤。提供了其上形成有种子层和具有开口的图案化光致抗蚀剂层的衬底。在开口中形成有覆盖种子层的底部的铜层。覆盖铜层的至少一个顶部的阻挡层形成在铜层上。阻挡层的氧化电位大于铜层的氧化电位。去除图案化的光致抗蚀剂层以进行蚀刻工艺，其中铜层和暴露的种子层的一部分被蚀刻以形成布线层。进行浸渍处理以在阻挡层和布线层的暴露表面上综合地形成抗氧化层。

45. 发明申请

US20100055843A1 CHIP PACKAGE MODULE HEAT SINK 审中-公开
标题翻译：芯片封装模块散热片
公开(公告)号：US20100055843A1
公开(公告)日：2010-03-04
申请号：US12615159
申请日：2009-11-09
申请人： Chien-Hung Liu
发明人： Chien-Hung Liu
IPC分类号： H01L21/00
CPC分类号： H01L23/3677 , H01L23/3114 , H01L2924/0002 , H01L2924/00
摘要： A heat sink mechanism including multiple heat passages in the base of a casing of a chip package module penetrating through a substrate packed in the module; a metal material being deposited in each heat passage to become a heat sink conductor connecting the substrate and the surface of the casing to effectively solve the problem of excessive heat generated in the course of HF operation of the chip package module thus to prevent chip failure.
摘要翻译：一种散热机构，包括穿过包装在所述模块中的基板的芯片封装模块的壳体的底部中的多个热通道; 沉积在每个热通道中的金属材料成为连接衬底和壳体表面的散热导体，以有效地解决芯片封装模块的HF操作过程中产生的过多热量的问题，从而防止芯片故障。

46. 发明公开

US20240109769A1 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20240109769A1
公开(公告)日：2024-04-04
申请号：US18538503
申请日：2023-12-13
申请人： Xintec Inc.
发明人： Wei-Luen SUEN , Jiun-Yen LAI , Hsing-Lung SHEN , Tsang-Yu LIU
IPC分类号： B81B7/00 , B81C1/00
CPC分类号： B81B7/0067 , B81C1/00317 , B81B2203/0353 , B81C2201/0125 , B81C2201/0132 , B81C2201/0194
摘要： A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

47. 发明公开

US20230361144A1 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20230361144A1
公开(公告)日：2023-11-09
申请号：US18304325
申请日：2023-04-20
申请人： Xintec Inc.
发明人： Wei-Ming CHIEN , Po-Han LEE , Tsang Yu LIU , Joey LAI
IPC分类号： H01L27/146
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14623
摘要： A chip package includes a light transmissive sheet, a chip, a bonding layer, and an insulating layer. The light transmissive sheet has a protruding portion. A first surface of the chip faces toward the light transmissive sheet and has a sensing area. The bonding layer is located between the chip and the light transmissive sheet. The sum of a thickness of the chip and a thickness of the bonding layer is greater than or equal to a thickness of the light transmissive sheet. A protruding portion of the light transmissive sheet protrudes from a sidewall of the chip and a sidewall of the bonding layer. The insulating layer extends from a second surface of the chip to the protruding portion of the light transmissive sheet along the sidewall of the chip and the sidewall of the bonding layer.

48. 发明申请

US20230049126A1 CHIP PACKAGE 有权
公开(公告)号：US20230049126A1
公开(公告)日：2023-02-16
申请号：US17980507
申请日：2022-11-03
申请人： XINTEC INC.
发明人： Chia-Ming CHENG , Shu-Ming CHANG
IPC分类号： H01L23/552 , H01L23/66 , H01L23/31 , H01L23/522 , H01L23/528 , H01L21/56
摘要： A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

49. 发明申请

US20220285423A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
公开(公告)号：US20220285423A1
公开(公告)日：2022-09-08
申请号：US17683917
申请日：2022-03-01
申请人： XINTEC INC.
发明人： Tsang-Yu LIU , Shu-Ming CHANG , Chaung-Lin LAI
IPC分类号： H01L27/146 , H01L23/544
摘要： Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

50. 发明申请

US20220157762A1 CHIP STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20220157762A1
公开(公告)日：2022-05-19
申请号：US17588185
申请日：2022-01-28
申请人： XINTEC INC.
发明人： Jiun-Yen LAI , Chia-Hsiang CHEN
IPC分类号： H01L23/00 , H01L23/48
摘要： A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

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