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41. 发明授权

US07477546B2 Non-volatile memory embedded in a conventional logic process and methods for operating same 失效
公开(公告)号：US07477546B2
公开(公告)日：2009-01-13
申请号：US12021255
申请日：2008-01-28
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

42. 发明申请

US20080159036A1 Scalable Embedded DRAM Array 有权
公开(公告)号：US20080159036A1
公开(公告)日：2008-07-03
申请号：US12048170
申请日：2008-03-13
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C7/02
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/104 , H01L27/10897
摘要： A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.

43. 发明授权

US07392456B2 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory 有权
标题翻译：在半导体存储器中促进高速字节写入的预测性纠错码产生
公开(公告)号：US07392456B2
公开(公告)日：2008-06-24
申请号：US10997604
申请日：2004-11-23
申请人： Wingyu Leung , Kit Sang Tam
发明人： Wingyu Leung , Kit Sang Tam
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.
摘要翻译：以实现错误代码校正的存储器系统中的部分字写入事务的预测方式生成写校验位。从存储器的地址读取读取数据字和相关联的读取校验位。如果读取数据字的一个字节存在错误，则识别该字节。同时，未校正的读取数据字的一个或多个字节与写入数据字的一个或多个字节合并，从而创建合并的数据字。响应于合并的数据字生成写校验位。如果合并的数据字包含包含错误的读取数据字的字节，则修改校验位以反映该错误。合并的数据字和修改的（或未修改的）写入校验位然后被写入存储器的地址。

44. 发明授权

US07391647B2 Non-volatile memory in CMOS logic process and method of operation thereof 失效
标题翻译： CMOS逻辑过程中的非易失性存储器及其操作方法
公开(公告)号：US07391647B2
公开(公告)日：2008-06-24
申请号：US11279382
申请日：2006-04-11
申请人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
发明人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C16/0416 , G11C16/10 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/7883
摘要： A non-volatile memory (NVM) cell fabricated on a semiconductor substrate, and including a floating gate electrode (which extends at least partially over all active regions of the NVM cell). The NVM cell also includes a PMOS access transistor located in a first n-type region, a PMOS control capacitor located in a second n-type region (separate from the first n-type region), and an NMOS programming transistor located in a p-type region. The floating gate electrode is a continuous electrode which extends over the active regions of the PMOS access transistor, the PMOS control capacitor and the NMOS programming transistor. Various array connections are provided for implementing arrays using this NVM cell. The PMOS access transistor and NMOS programming transistor can be replaced with an NMOS access transistor and a PMOS erase transistor, respectively, in an alternate embodiment.
摘要翻译：制造在半导体衬底上的非易失性存储器（NVM）单元，并且包括浮置栅极电极（至少部分地延伸到NVM单元的所有有源区域上）。 NVM单元还包括位于第一n型区域中的PMOS访问晶体管，位于第二n型区域（与第一n型区域分离）的PMOS控制电容器，以及位于p型区域中的NMOS编程晶体管型区域。浮置栅电极是在PMOS存取晶体管，PMOS控制电容器和NMOS编程晶体管的有源区域上延伸的连续电极。提供了各种阵列连接来实现使用该NVM单元的阵列。在替代实施例中，PMOS存取晶体管和NMOS编程晶体管可以分别被NMOS存取晶体管和PMOS擦除晶体管代替。

45. 发明授权

US07382658B2 Non-volatile memory embedded in a conventional logic process and methods for operating same 有权
标题翻译：嵌入在常规逻辑过程中的非易失性存储器及其操作方法
公开(公告)号：US07382658B2
公开(公告)日：2008-06-03
申请号：US11421986
申请日：2006-06-02
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C11/34 , G11C11/24
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.
摘要翻译：一种包括单元阵列的非易失性存储器系统，每个单元具有存取晶体管和共享浮置栅极的电容器。每行中的存取晶体管被制造在独立的偏置区域中。在每行内，每个存取晶体管的源极耦合到对应的虚拟接地线，并且每个电容器结构耦合到对应的字线。或者，列中的每个存取晶体管的源极耦合到相应的虚拟接地线。在每列中，每个存取晶体管的漏极耦合到相应的位线。选择每行的存储单元通过带对带隧道进行编程。位线偏置可防止对该行的非选定单元进行编程。通过控制这些行的阱区电压，在未选择的行中防止编程。扇区擦除操作由Fowler-Nordheim隧道实现。

46. 发明授权

US07323379B2 Fabrication process for increased capacitance in an embedded DRAM memory 失效
标题翻译：嵌入式DRAM存储器中增加电容的制造工艺
公开(公告)号：US07323379B2
公开(公告)日：2008-01-29
申请号：US11050988
申请日：2005-02-03
申请人： Dennis Sinitsky , Fu-Chieh Hsu
发明人： Dennis Sinitsky , Fu-Chieh Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11
摘要： An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.
摘要翻译：嵌入式存储器系统包括与深沟槽隔离隔离的动态随机存取存储器（DRAM）单元阵列和与浅沟槽隔离隔离的逻辑晶体管。每个DRAM单元包括存取晶体管和电容器结构。通过在深沟槽隔离区域中形成金属 - 电介质半导体（MOS）电容器来制造电容器结构。在深沟槽隔离中形成空腔，从而暴露衬底的侧壁区域。侧壁区域被掺杂，从而形成单元电容器的一个电极。在暴露的侧壁上形成栅介电层，并且在所得结构上沉积多晶硅层，从而填充空腔。图案化多晶硅层以形成存取晶体管的栅电极和在衬底的侧壁区域和上表面上延伸的电容器电极。

47. 发明授权

US6075720A Memory cell for DRAM embedded in logic 有权
标题翻译：嵌入逻辑的DRAM的存储单元
公开(公告)号：US6075720A
公开(公告)日：2000-06-13
申请号：US134488
申请日：1998-08-14
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： G11C5/14 , G11C8/08 , G11C11/4074 , G11C11/408 , H01L21/02 , H01L21/314 , H01L21/8242 , G11C11/24
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085 , G11C5/147 , G11C2207/104 , H01L27/1085 , H01L27/10873 , H01L28/91
摘要： A structure which stores charge useful in a DRAM provides small cell size and eliminates subthreshold leakage current of the access transistor in the cell. Hence this is highly suitable for use for instance in ASICs (applications specific integrated circuits) which are fabricated using "logic" circuit fabrication techniques which normally do not accommodate DRAM cells. The DRAM charge storage structure includes a p-channel access transistor and an n-doped well in a p-doped substrate, a p-channel charge storage capacitor with its source/drain directly connected to the source region of the access field effect transistor, a source of a voltage to the gate of the storage capacitor, and a voltage source connected to the wordline and thereby to the gate terminal of the access transistor which switches between two voltage levels.
摘要翻译：存储在DRAM中有用的电荷的结构提供小单元尺寸并消除单元中存取晶体管的亚阈值漏电流。因此，这非常适用于例如使用通常不容纳DRAM单元的“逻辑”电路制造技术制造的ASIC（专用集成电路）。 DRAM电荷存储结构包括p沟道存取晶体管和p掺杂衬底中的n掺杂阱，其源极/漏极直接连接到接近场效应晶体管的源极区的p沟道电荷存储电容器，到存储电容器的栅极的电压源和连接到字线的电压源，从而连接到在两个电压电平之间切换的存取晶体管的栅极端子。

48. 发明授权

US10320370B2 Methods and circuits for adjusting parameters of a transceiver 有权
公开(公告)号：US10320370B2
公开(公告)日：2019-06-11
申请号：US13728910
申请日：2012-12-27
申请人： MoSys, Inc.
发明人： Prashant Choudhary , Haidang Lin , Alvin Wang , Saman Behtash , Shaishav Desai
IPC分类号： H03K5/00 , H04L25/03
摘要： Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold.

49. 发明授权

US10084488B1 Chip-to-chip port coherency without overhead 有权
公开(公告)号：US10084488B1
公开(公告)日：2018-09-25
申请号：US15199982
申请日：2016-06-30
申请人： MoSys, Inc.
发明人： Scott A Irwin , Paul O. Jennings
IPC分类号： H04J3/04 , H04B1/00 , H04L12/935 , H04B3/50 , H04L12/46
CPC分类号： H04B3/50 , H04L49/30
摘要： A network system includes a first device and a second device coupled to each other that mux and demux data for LSL to HSL transitions. The muxing and demuxing function in the first and second device, respectively, use timing logic from an existing training protocol, such as link training (“LT”). Although LT is used for establishing links between two chips, and has no provision for maintaining port coherency for port-specific input data on one chip to port-specific output data on another chip, the LT does have a uniquely identifiable logic transition in a known data pattern used for LT that can be multi-purposed for syncing the muxing and demuxing of the two interfaced chips, using a predetermined port sequence on both chips to maintain coherency of port-specific data.

50. 发明授权

US09921755B2 Integrated main memory and coprocessor with low latency 有权
公开(公告)号：US09921755B2
公开(公告)日：2018-03-20
申请号：US14872137
申请日：2015-09-30
申请人： MoSys, Inc.
发明人： Michael J Miller , Jay B Patel , Michael J Morrison
IPC分类号： G06F9/38 , G06F3/06 , G06F12/00 , H04L29/12 , H04L29/08 , G06F12/0875 , G06F12/0895
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/067 , G06F9/3877 , G06F12/00 , G06F12/0875 , G06F12/0895 , G06F2212/1024 , G06F2212/452 , G06F2212/604 , H04L29/12 , H04L67/1017 , H04L67/2842
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines that process on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

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