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41. 发明申请

US20110266514A1 MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT 有权
标题翻译：包含碳纳米管织物元件和转向元件的存储单元
公开(公告)号：US20110266514A1
公开(公告)日：2011-11-03
申请号：US13182960
申请日：2011-07-14
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： H01L45/00 , B82Y99/00
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/025 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.
摘要翻译：提供了一种存储单元，所述存储单元包括具有垂直取向的p-i-n结的转向元件和碳纳米管织物。导向元件和碳纳米管织物电串联布置，整个存储单元形成在基板上。还提供其他方面。

42. 发明授权

US08040721B2 Creating short program pulses in asymmetric memory arrays 有权
标题翻译：在非对称存储器阵列中创建短程序脉冲
公开(公告)号：US08040721B2
公开(公告)日：2011-10-18
申请号：US12551546
申请日：2009-08-31
申请人： Tyler Thorp , Roy E. Scheuerlein
发明人： Tyler Thorp , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/72 , G11C2213/77
摘要： The present invention provides methods and apparatus for adjusting voltages of bit and word lines to create short programming pulses to program a memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, switching the first line from the first voltage to a second voltage, and switching the first line from the second voltage to the first voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results. The switching operations together may create a first pulse.
摘要翻译：本发明提供了用于调整位和字线的电压以产生编程脉冲以编程存储器单元的方法和装置。本发明可以包括将连接到存储器单元的第一线路从第一线路备用电压设置为第一电压，将连接到存储器单元的第二线路从第二线路待机电压充电到预定电压，将第一线路从第一电压到第二电压，并且将第一线路从第二电压切换到第一电压。第一电压和预定电压之间的电压差使得不对存储单元进行编程的安全电压。第二电压和预定电压之间的电压差使得可操作以编程存储器单元的编程电压结果。一起切换操作可以产生第一脉冲。

43. 发明申请

US20110210305A1 METHOD TO PROGRAM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT 有权
标题翻译：编程包含碳纳米管织物元件和转向元件的存储单元的方法
公开(公告)号：US20110210305A1
公开(公告)日：2011-09-01
申请号：US13083746
申请日：2011-04-11
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： H01L45/00 , H01L21/8239 , B82Y30/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/285 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L51/0048 , H01L51/0595 , Y10S977/742
摘要： A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.
摘要翻译：提供了一种编程碳纳米管存储单元的方法，其中存储单元包括第一导体，操舵元件，碳纳米管织物和第二导体，其中所述操舵元件和所述碳纳米管织物串联地电排列在第一导体和第二导体，并且其中整个碳纳米管存储单元形成在衬底上方，所述碳纳米管织物具有第一电阻率，所述方法包括在所述第一导体和所述第二导体之间施加第一电脉冲，其中在施加第一电气设备脉冲之后，碳纳米管织物具有第二电阻率，第二电阻率小于第一电阻率。还提供其他方面。

44. 发明授权

US08004919B2 Methods and apparatus for extending the effective thermal operating range of a memory 有权
标题翻译：扩展存储器的有效热操作范围的方法和装置
公开(公告)号：US08004919B2
公开(公告)日：2011-08-23
申请号：US12828846
申请日：2010-07-01
申请人： Tyler J. Thorp , Roy E. Scheuerlein
发明人： Tyler J. Thorp , Roy E. Scheuerlein
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C16/06
摘要： Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.
摘要翻译：提供了用于存储器集成电路（“IC”）的热调节的装置和系统。该装置和系统可以包括存储器IC上的热传感器和耦合到热传感器的加热元件。加热元件适于响应于来自热传感器的信号来加热存储器IC。还提供其他方面。

45. 发明授权

US07982209B2 Memory cell comprising a carbon nanotube fabric element and a steering element 有权
标题翻译：存储单元包括碳纳米管织物元件和转向元件
公开(公告)号：US07982209B2
公开(公告)日：2011-07-19
申请号：US11692148
申请日：2007-03-27
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： H01L29/06
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/025 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.
摘要翻译：公开了一种可重写的非易失性存储单元，其包括与碳纳米管织物串联的转向元件。转向元件优选为二极管，但也可以是晶体管。当经受适当的电脉冲时，碳纳米管织物可逆地改变电阻率。可以感测碳纳米管织物的不同电阻率状态，并且可以对应于存储器单元的不同数据状态。这种存储器单元的第一存储器级别可以单片地形成在衬底上方，第一存储器级单元形成在第一存储器之上，等等，形成堆叠存储器级别的高密度单片三维存储器阵列。

46. 发明授权

US07961494B2 Non-volatile multi-level re-writable memory cell incorporating a diode in series with multiple resistors and method for writing same 有权
标题翻译：包含与多个电阻器串联的二极管的非易失性多电平可重写存储器单元及其写入方法
公开(公告)号：US07961494B2
公开(公告)日：2011-06-14
申请号：US12242417
申请日：2008-09-30
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C17/16 , G11C2013/009 , G11C2213/15 , G11C2213/19 , G11C2213/31 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/72 , Y10T29/49002
摘要： A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than “tuning” the resistance of a single resistive element. An exemplary memory cell includes a vertical pillar diode in series with two different bi-stable resistance films. Each bi-stable resistance film has both a high resistance and low resistance state that can be switched with appropriate application of a suitable bias voltage and current. Such a cross-point array is adaptable for two-dimensional rewritable memory arrays, and also particularly well-suited for three-dimensional rewritable (3D R/W) memory arrays.
摘要翻译：描述了多级读/写两端存储单元的非常密集的交叉点存储器阵列及其编程方法。使用两个或更多个具有双稳态电阻率状态的膜而不是“调谐”单个电阻元件的电阻来实现多个状态。示例性存储单元包括与两个不同的双稳电阻膜串联的立柱二极管。每个双稳态电阻膜具有高电阻和低电阻状态，可以适当地施加适当的偏置电压和电流来切换。这种交叉点阵列适用于二维可重写存储器阵列，并且还特别适用于三维可重写（3D R / W）存储器阵列。

47. 发明授权

US07924602B2 Method to program a memory cell comprising a carbon nanotube fabric element and a steering element 失效
标题翻译：对包含碳纳米管织物元件和转向元件的存储单元进行编程的方法
公开(公告)号：US07924602B2
公开(公告)日：2011-04-12
申请号：US12693782
申请日：2010-01-26
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/285 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L51/0048 , H01L51/0595 , Y10S977/742
摘要： A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.
摘要翻译：提供了一种编程碳纳米管存储单元的方法，其中存储单元包括第一导体，操舵元件，碳纳米管织物和第二导体，其中所述操舵元件和所述碳纳米管织物串联地电排列在第一导体和第二导体，并且其中整个碳纳米管存储单元形成在衬底上方，所述碳纳米管织物具有第一电阻率，所述方法包括在所述第一导体和所述第二导体之间施加第一电脉冲，其中在施加第一电气设备脉冲之后，碳纳米管织物具有第二电阻率，第二电阻率小于第一电阻率。还提供其他方面。

48. 发明申请

US20110051505A1 REDUCING PROGRAMMING TIME OF A MEMORY CELL 有权
标题翻译：减少存储单元的编程时间
公开(公告)号：US20110051505A1
公开(公告)日：2011-03-03
申请号：US12551548
申请日：2009-08-31
申请人： Tyler Thorp , Roy E. Scheuerlein
发明人： Tyler Thorp , Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C8/08 , G11C13/0004 , G11C13/0023 , G11C13/0061 , G11C13/0069
摘要： The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.
摘要翻译：本发明提供了调节位和字线的电压以编程两个终端存储单元的方法和装置。本发明可以包括将连接到存储器单元的第一线路从第一线路待机电压设置为第一电压，将连接到存储器单元的第二线路从第二线路待机电压充电到预定电压，以及将第一线路从第一电压到第二电压。第一电压和预定电压之间的电压差使得不对存储单元进行编程的安全电压。第二电压和预定电压之间的电压差使得可操作以编程存储器单元的编程电压结果。

49. 发明申请

US20110019495A1 DECODER CIRCUITRY PROVIDING FORWARD AND REVERSE MODES OF MEMORY ARRAY OPERATION AND METHOD FOR BIASING SAME 有权
标题翻译：提供存储器阵列操作的前向和反向模式的解码器电路及其偏移方法
公开(公告)号：US20110019495A1
公开(公告)日：2011-01-27
申请号：US12895523
申请日：2010-09-30
申请人： Roy E. Scheuerlein , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Luca G. Fasoli
IPC分类号： G11C8/10 , G11C8/08
CPC分类号： G11C7/18 , G11C7/1048 , G11C8/08 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

50. 发明授权

US07773443B2 Current sensing method and apparatus for a memory array 有权
标题翻译：用于存储器阵列的电流感测方法和装置
公开(公告)号：US07773443B2
公开(公告)日：2010-08-10
申请号：US12405160
申请日：2009-03-16
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/025 , G11C7/067 , G11C7/18 , G11C8/08 , G11C8/10 , G11C17/18 , G11C2207/063
摘要： A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
摘要翻译：存储器阵列包括用于感测位线电流的感测电路，同时保持所选位线的电压基本上不变。字线和位线被偏置，使得基本上不会在半选择的存储器单元上施加偏置电压，这几乎消除了通过半选择的存储器单元的泄漏电流。感测的位线电流很大程度上仅来自所选存储单元的电流。存储器阵列中的噪声检测线减少了从未选择的字线耦合到所选位线的影响。在优选实施例中，具有在多于一个层上形成位线的多个轨道堆叠的三维存储器阵列包括与每个位线层相关联的至少一个噪声检测线。感测电路连接到选定的位线及其相关的噪声检测线。

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