专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20050189653A1 Dual damascene intermediate structure and method of fabricating same 审中-公开
标题翻译：双镶嵌中间结构及其制造方法
公开(公告)号：US20050189653A1
公开(公告)日：2005-09-01
申请号：US10872946
申请日：2004-06-21
申请人： Hun-Jan Tao , Chao-Cheng Chen
发明人： Hun-Jan Tao , Chao-Cheng Chen
IPC分类号： H01L21/768 , H01L23/48 , H01L23/522 , H01L29/40
CPC分类号： H01L21/76808 , H01L21/76804 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An intermediate structure from which a dual damascene structure may be fabricated includes a first-formed, unfaceted via hole and an intersecting trench both formed by gas plasma etching of a dielectric layer. The sidewall of the via hole is maintained unfaceted during and after trench formation by substantially filling it with a gas-plasma-etchable plug prior to trench formation. The presence of the plug in the via hole during gas plasma etching of the trench, also produces a trench bottom that is substantially flat.
摘要翻译：可以制造双镶嵌结构的中间结构包括通过电介质层的气体等离子体蚀刻形成的第一形成的非平行通孔和交叉沟槽。在沟槽形成期间和之后通孔的侧壁通过在沟槽形成之前用气体等离子体可蚀刻的塞子基本上填充而保持不通气。在沟槽的气体等离子体蚀刻期间，插塞在通孔中的存在也产生基本上平坦的沟槽底部。

42. 发明申请

US20050164506A1 Method and apparatus for backside polymer reduction in dry-etch process 有权
标题翻译：用于干蚀刻工艺中背面聚合物还原的方法和装置
公开(公告)号：US20050164506A1
公开(公告)日：2005-07-28
申请号：US10765808
申请日：2004-01-27
申请人： Huang-Ming Chen , Chun-Li Chou , Chao-Cheng Chen , Hun-Jan Tao
发明人： Huang-Ming Chen , Chun-Li Chou , Chao-Cheng Chen , Hun-Jan Tao
IPC分类号： H01J37/32 , H01L21/00 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/461 , H01L21/687
CPC分类号： H01L21/68735 , H01J37/3244 , H01J37/32642 , H01L21/02046 , H01L21/31116 , H01L21/67069 , Y10S156/914 , Y10S156/915 , Y10T279/23
摘要： A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.
摘要翻译：防止在半导体衬底的背面形成污染性聚合物膜的方法包括提供在蚀刻操作期间释放氧气的氧浸渍聚焦环和/或氧浸渍卡盘。该方法还通过在冷却气体混合物中混合氧将氧气输送到衬底，在蚀刻和清洁衬底期间将聚焦环保持在不高于衬底温度的温度，使用包括悬浮衬底的两步骤等离子体清洗序列在卡盘上方

43. 发明授权

US06914007B2 In-situ discharge to avoid arcing during plasma etch processes 有权
标题翻译：原位放电以避免等离子体蚀刻过程中的电弧
公开(公告)号：US06914007B2
公开(公告)日：2005-07-05
申请号：US10366206
申请日：2003-02-13
申请人： Ching-Hui Ma , Chao-Cheng Chen , Tsang-Jiuh Wu , Hui-Chang Yu , Hun-Jan Tao
发明人： Ching-Hui Ma , Chao-Cheng Chen , Tsang-Jiuh Wu , Hui-Chang Yu , Hun-Jan Tao
IPC分类号： H01L21/311 , H01L21/768 , H01L21/302 , H01L21/461 , H01L21/462
CPC分类号： H01J37/32009 , H01J2237/0206 , H01L21/31116 , H01L21/76802
摘要： A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CXFYHZ or a fluorocarbon and a gas such as O2, H2, N2, N2O, CO, CO2, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.
摘要翻译：描述了一种减少衬底上的电荷以防止在后续蚀刻工艺中的电弧入射的方法。图案化衬底被固定到处理室中的卡盘。执行放电处理，其包括以下三个步骤：（a）将卡盘耦合到0伏连接，（b）产生等离子体，以及（c）将卡盘耦合到高压连接。三个步骤以任何顺序进行。在放电顺序期间，惰性气体或惰性气体和蚀刻气体流入腔室。或者，碳氟化合物C 1 H Z，或碳氟化合物和气体如O 2 H，H N 2，N 2，N 2 O，CO，CO 2，He或Ar流入室在放电序列期间。该方法与批次或单晶片工艺兼容，并且可扩展到蚀刻导热性差的低k电介质层。

44. 发明授权

US06440863B1 Plasma etch method for forming patterned oxygen containing plasma etchable layer 有权
标题翻译：用于形成图案化含氧等离子体可刻蚀层的等离子体蚀刻方法
公开(公告)号：US06440863B1
公开(公告)日：2002-08-27
申请号：US09148556
申请日：1998-09-04
申请人： Chia-Shiun Tsai , Chao-Cheng Chen , Hun-Jan Tao
发明人： Chia-Shiun Tsai , Chao-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01L21/7681 , H01L21/31116 , H01L21/31138 , H01L21/76808 , H01L2221/1031 , H01L2221/1036
摘要： A method for forming a patterned oxygen containing plasma etchable layer. There is first provided a substrate. There is then formed upon the substrate a blanket oxygen containing plasma etchable layer. There is then formed upon the blanket oxygen containing plasma etchable layer a blanket hard mask layer. There is then formed upon the blanket hard mask layer a patterned photoresist layer. There is then etched while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer the blanket hard mask layer to form a patterned hard mask layer. There is then etched while employing a second plasma etch method in conjunction with at least the patterned hard mask layer as a second etch mask layer the blanket oxygen containing plasma etchable layer to form a patterned oxygen containing plasma etchable layer. The second plasma etch method employs a second etchant gas composition comprising: (1) an oxygen containing etchant gas which upon plasma activation provides an active oxygen etching species; and (2) boron trichloride.
摘要翻译：一种用于形成图案化含氧等离子体可刻蚀层的方法。首先提供基板。然后在衬底上形成包含氧气的等离子体可蚀刻层。然后在橡皮布含氧等离子体可蚀刻层上形成橡皮布硬掩模层。然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层。然后蚀刻，同时采用第一等离子体蚀刻方法结合图案化的光致抗蚀剂层作为第一蚀刻掩模层，橡皮布硬掩模层以形成图案化的硬掩模层。然后蚀刻，同时采用第二等离子体蚀刻方法结合至少图案化的硬掩模层作为第二蚀刻掩模层，该覆盖氧含氧等离子体可蚀刻层以形成图案化的含氧等离子体可蚀刻层。第二等离子体蚀刻方法采用第二蚀刻剂气体组合物，其包括：（1）含氧蚀刻剂气体，其在等离子体激活时提供活性氧蚀刻物质; 和（2）三氯化硼。

45. 发明授权

US06429119B1 Dual damascene process to reduce etch barrier thickness 有权
标题翻译：双镶嵌工艺减少蚀刻阻挡层厚度
公开(公告)号：US06429119B1
公开(公告)日：2002-08-06
申请号：US09405059
申请日：1999-09-27
申请人： Li-Chih Chao , Chia-Shiung Tsai , Ming-Huei Lui , Jen-Cheng Liu , Chao-Cheng Chen
发明人： Li-Chih Chao , Chia-Shiung Tsai , Ming-Huei Lui , Jen-Cheng Liu , Chao-Cheng Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76813 , H01L2221/1063
摘要： Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.
摘要翻译：使用这种特殊的双镶嵌工艺，形成具有低寄生电容（低RC时间常数）的互连导线和通孔触点。本发明包括使用薄蚀刻停止层或蚀刻阻挡层。本发明的关键工艺步骤是特殊的部分通孔蚀刻和特殊通孔衬垫。现有技术的双镶嵌工艺通常由厚的通孔蚀刻停止层组成，以避免在通孔图案化期间损坏下面的铜，以及在沟槽图案化期间避免通孔小面的厚沟槽蚀刻停止层。与氧化硅（金属间电介质（IMD））相比，由于高的介电常数值，厚的蚀刻停止层是不期望的。因此，应该减小停止层的厚度以最小化电路（RC）时间常数延迟。一般来说，双镶嵌蚀刻有两种主要方法。主要方法之一使用自对准双镶嵌（SADD）蚀刻，其需要厚沟槽蚀刻停止层厚度。另一种方法使用需要厚通孔蚀刻停止层厚度的反孔法。本发明描述了一种新颖的双镶嵌工艺，其可以最小化通孔和沟槽蚀刻停止层的厚度，同时避免在通孔和沟槽蚀刻期间对于底面和经过小面轮廓的有害损伤。

46. 发明授权

US06319822B1 Process for forming an integrated contact or via 有权
标题翻译：用于形成集成接触或通孔的工艺
公开(公告)号：US06319822B1
公开(公告)日：2001-11-20
申请号：US09164999
申请日：1998-10-01
申请人： Chao-Cheng Chen , Chia-Shiung Tsai , Shau-Lin Shue , Hun-Jan Tao
发明人： Chao-Cheng Chen , Chia-Shiung Tsai , Shau-Lin Shue , Hun-Jan Tao
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/0332 , H01L21/0335 , H01L21/31116 , H01L21/31122 , H01L21/31144 , H01L21/76802
摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer. The protective sidewall polymer inhibits lateral chemical etching and results in openings with smooth, straight, and near-vertical sidewalls without loss of dimensional integrity.
摘要翻译：描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。该方法使用由富碳氮化钛形成的硬掩模。硬掩模在相对较厚的绝缘层中对蚀刻接触和通孔的选择性很高。高选择性需要相对薄的硬掩模，其可以通过薄的光致抗蚀剂掩模容易地图案化，使得该工艺对于DUV光刻非常期望。硬掩模由MOCVD使用金属有机钛前体形成。通过适当选择MOCVD沉积条件，将受控量的碳纳入TiN膜中。在等离子体蚀刻期间，随着硬掩模腐蚀而释放碳，并且参与沿着在绝缘层中蚀刻的开口的侧壁形成保护性聚合物涂层。保护性侧壁聚合物抑制侧向化学蚀刻并导致具有平滑，直的和近垂直的侧壁的开口，而不损失尺寸完整性。

47. 发明授权

US6025273A Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask 失效
标题翻译：用于使用碳掺杂的硬掩模来蚀刻具有改进的半导体集成电路的轮廓的可靠的小接触孔的方法
公开(公告)号：US6025273A
公开(公告)日：2000-02-15
申请号：US55433
申请日：1998-04-06
申请人： Chao-Cheng Chen , Chia-Shiung Tsai , Hun-Jan Tao
发明人： Chao-Cheng Chen , Chia-Shiung Tsai , Hun-Jan Tao
IPC分类号： H01L21/033 , H01L21/311 , H01L21/768 , H01L23/522 , H01L21/283
CPC分类号： H01L21/31144 , H01L21/76816 , H01L23/5226 , H01L21/0332 , H01L21/31116 , H01L2924/0002
摘要： A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F.sup.+) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O.sub.2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.
摘要翻译：实现了用于在用于集成电路的层间电介质（ILD）层中制造小接触孔的方法。该方法增加了ILD蚀刻速率，同时减少了接触孔侧壁上的残留物积聚。这提供了使接触孔宽度小于0.25μm的非常理想的方法。在包括图案化掺杂的第一多晶硅层的部分完成的集成电路上沉积ILD层之后，通过离子注入沉积第二多晶硅层并掺杂碳。光致抗蚀剂掩模用于蚀刻碳掺杂多晶硅层中的开口以形成硬掩模。去除光致抗蚀剂，并且在ILD层中对接触孔进行等离子体蚀刻，而在蚀刻期间从硬掩模释放出的游离碳降低了等离子体中的游离氧。这导致ILD层中的接触孔的氟（F +）蚀刻速率增加，并减少了接触孔的侧壁上的残留物积聚。硬掩模在O 2中退火以形成氧化物层，并且在湿蚀刻中除去任何表面碳。现在可以通过沉积诸如钛（Ti）或氮化钛（TiN）和诸如钨（W）的金属的阻挡层并且将氧化物层回蚀刻或化学/机械抛光来形成可靠的金属插塞。

48. 发明授权

US6008131A Bottom rounding in shallow trench etching using a highly isotropic etching step 失效
标题翻译：使用高度各向同性的蚀刻步骤在浅沟槽蚀刻中进行底部圆整处理
公开(公告)号：US6008131A
公开(公告)日：1999-12-28
申请号：US995340
申请日：1997-12-22
申请人： Chao-Cheng Chen
发明人： Chao-Cheng Chen
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/302
CPC分类号： H01L21/3065 , H01L21/76232
摘要： A method of forming shallow isolation trenches in integrated circuit wafers which prevents wafer damage due to dislocations or the like occurring at sharp corners at the intersection between the sidewalls and bottom of the trench. A trench is formed in the wafer using a series of reactive ion etching steps. The bottom of the trench is then etched using reactive ion etching with etching parameters chosen to produce dry isotropic etching. The dry isotropic etching of the bottom of the trench results in a rounded bottom and sharp corners between the sidewalls and bottom of the trench are avoided.
摘要翻译：在集成电路晶片中形成浅隔离沟槽的方法，其防止由于在沟槽的侧壁和底部之间的交叉处的尖角处发生位错等的晶片损坏。使用一系列反应离子蚀刻步骤在晶片中形成沟槽。然后使用反应离子蚀刻蚀刻沟槽的底部，并且选择蚀刻参数以产生干各向同性蚀刻。沟槽底部的干各向同性腐蚀导致圆形的底部，并避免了沟槽的侧壁和底部之间的尖角。

49. 发明授权

US5994229A Achievement of top rounding in shallow trench etch 失效
标题翻译：在浅沟槽蚀刻中取得顶尖圆角的成就
公开(公告)号：US5994229A
公开(公告)日：1999-11-30
申请号：US5567
申请日：1998-01-12
申请人： Chao-Cheng Chen , Chia-Shiung Tsai
发明人： Chao-Cheng Chen , Chia-Shiung Tsai
IPC分类号： H01L21/3065 , H01L21/762
CPC分类号： H01L21/3065 , H01L21/76232
摘要： A process for forming a shallow trench having steep sidewalls near its bottom and sloping sidewalls at the top is described. The process is in 3 stages. The first stage involves methane trifluoride, carbon tetrafluoride, argon, and oxygen. The second stage involves methane trifluoride and methane monofluoride, while the third stage involves hydrogen bromide, chlorine, and helium/oxygen. If the ratio of the various components at each stage is carefully controlled along with other variables such as discharge power, pressure, and duration, the trench profile described above is obtained with a minimum of deposited polymer material on the sidewalls.
摘要翻译：描述了一种用于形成在其底部附近具有陡峭侧壁并且在顶部具有倾斜侧壁的浅沟槽的工艺。这个过程分3个阶段。第一阶段涉及三氟化甲烷，四氟化碳，氩气和氧气。第二阶段涉及甲烷三氟化氢和甲烷单氟化物，而第三阶段涉及溴化氢，氯气和氦气/氧气。如果每个阶段的各种组分的比例与诸如放电功率，压力和持续时间的其他变量一起被仔细地控制，则上述的沟槽轮廓是通过在侧壁上沉积的最少的聚合物材料获得的。

50. 发明授权

US5981398A Hard mask method for forming chlorine containing plasma etched layer 失效
标题翻译：用于形成含氯等离子体蚀刻层的硬掩模方法
公开(公告)号：US5981398A
公开(公告)日：1999-11-09
申请号：US58122
申请日：1998-04-10
申请人： Chia-Shiung Tsai , Chao-Cheng Chen , Hun-Jan Tao
发明人： Chia-Shiung Tsai , Chao-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/3213 , H01L21/3065
CPC分类号： H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer. Finally, there is then etched while employing at least the patterned hard mask layer as a second etch mask layer and while employing the second plasma employing the chlorine containing etchant gas composition the blanket target layer to form the patterned target layer.
摘要翻译：一种形成含氯等离子体蚀刻图案层的方法。首先提供了在微电子制造中使用的衬底10。然后在衬底上形成由使用含氯蚀刻剂气体组合物在第二等离子体内易于蚀刻的材料形成的覆盖层目标层12。然后在橡皮布目标上形成由选自倍半硅氧烷旋涂玻璃（SOG）材料和无定形碳材料的材料形成的橡皮布硬掩模层14。然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层16.然后在使用图案化的光致抗蚀剂层作为第一蚀刻掩模层的同时进行蚀刻，并且在使用含氟蚀刻剂气体组合物的第一等离子体的同时，以形成图案化的硬掩模层。最后，在使用至少图案化的硬掩模层作为第二蚀刻掩模层的同时蚀刻，并且在使用含氯蚀刻剂气体组合物的第二等离子体时，覆盖目标层以形成图案化目标层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式