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41. 发明授权

US4914630A Refresh arrangement in a block divided memory including a plurality of shift registers 失效
标题翻译：在包括多个移位寄存器的块分割存储器中的刷新布置
公开(公告)号：US4914630A
公开(公告)日：1990-04-03
申请号：US192714
申请日：1988-05-11
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Hideto Hidaka
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Hideto Hidaka
IPC分类号： G11C11/401 , G11C8/12 , G11C11/406 , G11C11/407 , G11C11/409
CPC分类号： G11C11/406 , G11C8/12
摘要： In a block access memory, the memory cell array is divided into a plurality of blocks, one word line is selected based on the external address and the access to the memory cells connected thereto is carried out in one block and, simultaneously, one word line is selected based on the internally generated refresh address and the refresh of the memory cells connected to the word line is carried out in the other block.
摘要翻译：在块访问存储器中，存储单元阵列被划分为多个块，一个字线基于外部地址被选择，并且在一个块中执行对与其连接的存储器单元的访问，同时，一个字线是基于内部产生的刷新地址来选择的，并且在另一块中执行连接到字线的存储器单元的刷新。

42. 发明授权

US5550769A Bit line structure for semiconductor memory device 失效
公开(公告)号：US5550769A
公开(公告)日：1996-08-27
申请号：US336114
申请日：1994-11-04
申请人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
发明人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
IPC分类号： G11C5/06 , G11C7/18 , G11C11/24
CPC分类号： G11C5/063 , G11C7/18
摘要： A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

43. 发明授权

US5509132A Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 失效
标题翻译：具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法
公开(公告)号：US5509132A
公开(公告)日：1996-04-16
申请号：US283487
申请日：1994-08-01
申请人： Yoshio Matsuda , Kazuyasu Fujishima , Hideto Hidaka , Mikio Asakura
发明人： Yoshio Matsuda , Kazuyasu Fujishima , Hideto Hidaka , Mikio Asakura
IPC分类号： G06F12/08 , G11C7/10 , G11C8/00 , G11C11/401 , G11C11/41
CPC分类号： G06F12/0893 , G11C7/1051
摘要： A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.
摘要翻译：缓存DRAM（100）包括通过行地址信号和列地址信号访问的DRAM存储器阵列（11），由列地址信号访问的SRAM存储器阵列（21）和ECC电路（30）。 DRAM存储器阵列（11）被分成多个块（B1至B64），每个块包括多个列。 SRAM存储器阵列（21）包括4路（W1至W4）。在确定高速缓存命中/高速缓存未命中时，输入列地址信号。因此，访问SRAM存储器阵列（21）并且从每种方式读取数据。当发生高速缓存命中时，响应于外部施加的方式地址信号选择一种方式，并且从该方式输出数据。当发生高速缓存未命中时，锁存列地址信号并应用行地址信号。根据行地址信号和锁存列地址信号来访问DRAM阵列（11）。

44. 发明授权

US5416734A Bit line structure for semiconductor memory device 失效
标题翻译：半导体存储器件的位线结构
公开(公告)号：US5416734A
公开(公告)日：1995-05-16
申请号：US28917
申请日：1993-03-08
申请人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
发明人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
IPC分类号： G11C5/06 , G11C7/18 , G11C11/24
CPC分类号： G11C5/063 , G11C7/18
摘要： A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.
摘要翻译：一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

45. 发明授权

US5226139A Semiconductor memory device with a built-in cache memory and operating method thereof 失效
标题翻译：具有内置缓存存储器的半导体存储器件及其操作方法
公开(公告)号：US5226139A
公开(公告)日：1993-07-06
申请号：US637872
申请日：1991-01-08
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Hideto Hidaka , Mikio Asakura
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Hideto Hidaka , Mikio Asakura
IPC分类号： G06F9/38 , G06F12/08 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/41
CPC分类号： G06F9/3824 , G06F12/0893 , G11C11/408 , G11C11/4096
摘要： A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address signals (B0, B1) and a column address signal (CA) are simultaneously applied. Any of the plurality of blocks (B1 to B16) is selected in response to the block address signals (B0, B1). At the same time, any of the plurality of registers (16a) corresponding to the selected block is selected in response to the column address signal (CA). The data stored in the register (16a) is thereby read out at a high speed
摘要翻译：具有内置高速缓冲存储器的半导体存储器件包括存储单元阵列（1）。存储单元阵列（1）被分成多个块（B1〜B16）。每个块被分成多个子块，每个子块具有多个列。在缓存命中时，同时施加块地址信号（B0，B1）和列地址信号（CA）。响应于块地址信号（B0，B1）选择多个块（B1至B16）中的任一个。同时，响应于列地址信号（CA）选择对应于所选块的多个寄存器（16a）中的任何一个。因此，存储在寄存器（16a）中的数据被高速读出

46. 发明授权

US5222047A Method and apparatus for driving word line in block access memory 失效
标题翻译：用于在块存取存储器中驱动字线的方法和装置
公开(公告)号：US5222047A
公开(公告)日：1993-06-22
申请号：US566809
申请日：1990-08-13
申请人： Yoshio Matsuda , Kazuyasu Fujishima , Hideto Hidaka
发明人： Yoshio Matsuda , Kazuyasu Fujishima , Hideto Hidaka
IPC分类号： G11C7/10 , G11C8/14 , G11C8/18
CPC分类号： G11C8/14 , G11C7/1036 , G11C7/1039 , G11C8/18 , H01L2924/01074
摘要： In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.
摘要翻译：在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。

47. 发明授权

US5179687A Semiconductor memory device containing a cache and an operation method thereof 失效
标题翻译：包含高速缓存的半导体存储器件及其操作方法
公开(公告)号：US5179687A
公开(公告)日：1993-01-12
申请号：US542682
申请日：1990-06-25
申请人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
发明人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0893 , G11C11/4096
摘要： A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory cell array. Upon cache hit, the row address strobe signal is inactivated to cause the selector to select the access to the data registers. Upon cache miss, the row address strobe signal is activated to cause the selector to select the access to the memory cell array.
摘要翻译：用于简单高速缓冲存储器系统的DRAM包括被划分成多个块的存储单元阵列，与阵列的各个块对应地提供的多个数据寄存器，用于锁存相应块的存储单元数据，以及响应于选择器用于选择对数据寄存器或存储单元阵列的访问的行地址选通信号。缓存命中后，行地址选通信号被取消激活，使选择器选择对数据寄存器的访问。在缓存未命中时，行地址选通信号被激活以使选择器选择对存储单元阵列的访问。

48. 发明授权

US06404691B1 Semiconductor memory device for simple cache system 失效
标题翻译：半导体存储器件，用于简单缓存系统
公开(公告)号：US06404691B1
公开(公告)日：2002-06-11
申请号：US08472770
申请日：1995-06-07
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
摘要翻译：一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。在缓存命中时，数据被访问到SRAM存储单元阵列。在缓存未命中时，数据被存取到DRAM存储单元阵列。在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

49. 发明授权

US5226147A Semiconductor memory device for simple cache system 失效
标题翻译：半导体存储器件，用于简单缓存系统
公开(公告)号：US5226147A
公开(公告)日：1993-07-06
申请号：US564657
申请日：1990-08-09
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
IPC分类号： G06F12/08 , G11C7/10
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
摘要翻译：一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。在缓存命中时，数据被访问到SRAM存储单元阵列。在缓存未命中时，数据被存取到DRAM存储单元阵列。在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

50. 发明授权

US5214601A Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers 失效
标题翻译：包括交叉点和多个互连层的半导体存储器件的位线结构
公开(公告)号：US5214601A
公开(公告)日：1993-05-25
申请号：US876690
申请日：1992-04-28
申请人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
发明人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
IPC分类号： G11C5/06 , G11C7/18
CPC分类号： G11C5/063 , G11C7/18
摘要： A semiconductor memory device of folded bit line structure includes a cross portion in at least one portion of each bit line pair so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N (N being an integer), although advantages of the invention may be obtained with division of the bit lines into 3N, and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. In a preferred embodiment, the cross parts are provided in regions for forming restore circuits or sense amplifiers. In a further embodiment, a dummy word line for selecting dummy cells for providing a reference potential is selected according to the position of a selected word line.
摘要翻译：折叠位线结构的半导体存储器件包括每个位线对的至少一部分中的交叉部分，使得与相邻位线对的耦合电容值相对于成对的位线彼此相等。优选地，各位线对被均等地划分为4N（N是整数），尽管可以通过将位线划分为3N来获得本发明的优点，并且在分割点处提供交叉部分，使得位线对将相同分割点处的交叉部分布置在交替的位线对上。在优选实施例中，交叉部分设置在用于形成恢复电路或感测放大器的区域中。在另一实施例中，根据所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

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