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    • 43. 发明授权
    • Semiconductor integrated circuit device and fabrication method thereof
    • 半导体集成电路器件及其制造方法
    • US07930658B2
    • 2011-04-19
    • US12285073
    • 2008-09-29
    • Keiichi Yoshioka
    • Keiichi Yoshioka
    • G06F17/50G06F19/00H03K17/16H03K19/003H01L25/00H01L21/70H01L27/088H01L23/10
    • G06F17/5068H01L27/11803H01L27/1203
    • A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor element is formed on a support substrate. The multi-layer wiring structure is formed in an insulation film on the support substrate and includes at least one connection hole and at least one metal wiring layer. The heat conduction part is formed of the same conductive materials as the connection hole and the metal wiring layer and extends toward an upper layer side along a path different from a wiring path including a connection hole and a metal wiring for signal transmission.
    • 公开了一种半导体集成电路器件及其制造方法,用于有效抑制由半导体元件的发热引起的温度升高。 半导体集成电路器件包括半导体元件,多层布线结构和导热部分。 半导体元件形成在支撑基板上。 多层布线结构形成在支撑基板上的绝缘膜中,并且包括至少一个连接孔和至少一个金属布线层。 导热部分由与连接孔和金属布线层相同的导电材料形成,并且沿着与包括连接孔和用于信号传输的金属布线的布线路径不同的路径向上层侧延伸。
    • 50. 发明授权
    • Information processing apparatus
    • 信息处理装置
    • US5896515A
    • 1999-04-20
    • US582670
    • 1996-01-04
    • Hideyuki AotaKeiichi Yoshioka
    • Hideyuki AotaKeiichi Yoshioka
    • G06F9/34G06F9/30G06F12/06
    • G06F9/3012G06F9/30101G06F9/30141
    • A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to the central processing unit. An output signal of an address circuit included in the central processing unit is supplied to the register-bank memory. Alternatively, an output signal of a decoding circuit included in the central processing unit may be supplied to the register-bank memory. A signal for selecting either activation or deactivation of the register-bank memory is a signal which indicates a selection of the deactivation of the register-bank memory except in a case where data is written in the general-use register set and a case of a restoration operation after register bank switching. Instead, a signal for selecting either generating or non-generating of a clock signal for the register-bank memory may be a signal which indicates a selection of the non-generation of the clock signal for the register-bank memory except in a case where data is written in the general-use register set and in a case of a restoration operation after register bank switching.
    • 通用寄存器组包括在中央处理单元主体中的多个寄存器。 寄存器组存储器具有与多个寄存器相关的存储器区域,并且连接到中央处理单元。 包括在中央处理单元中的地址电路的输出信号被提供给寄存器组存储器。 或者,包括在中央处理单元中的解码电路的输出信号可以被提供给寄存器组存储器。 用于选择寄存器组存储器的激活或去激活的信号是指示除了在通用寄存器组中写入数据的情况下的寄存器组存储器的去激活的选择的信号,以及 寄存器组切换后的恢复操作。 相反,用于选择产生或不产生用于寄存器组存储器的时钟信号的信号可以是指示对于寄存器组存储器的非时钟信号的选择的信号,除了在 数据被写入通用寄存器组中,并且在寄存器组切换之后的恢复操作的情况下。