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41. 发明授权

US07816735B2 Integrated circuit devices including a transcription-preventing pattern 失效
标题翻译：集成电路装置，包括转录阻止图案
公开(公告)号：US07816735B2
公开(公告)日：2010-10-19
申请号：US11974293
申请日：2007-10-12
申请人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , InSoo Jung
发明人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , InSoo Jung
IPC分类号： H01L33/16
CPC分类号： H01L21/823425 , H01L21/823475
摘要： Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
摘要翻译：在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。绝缘层图案在其中具有部分地暴露第一单晶层的开口。种子层在开口处。第二单晶层位于绝缘层图案和籽晶层上。第二单晶层具有与种子层基本相同的晶体结构。转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

42. 发明授权

US06963094B2 Metal oxide semiconductor transistors having a drain punch through blocking region and methods for fabricating metal oxide semiconductor transistors having a drain punch through blocking region 有权
标题翻译：具有漏极穿通阻挡区域的金属氧化物半导体晶体管和用于制造具有漏极穿通阻挡区域的金属氧化物半导体晶体管的方法
公开(公告)号：US06963094B2
公开(公告)日：2005-11-08
申请号：US10394338
申请日：2003-03-21
申请人： Byeong-Chan Lee , Si-Young Choi , Chul-Sung Kim , Jong-Ryeol Yoo , Deok-Hyung Lee
发明人： Byeong-Chan Lee , Si-Young Choi , Chul-Sung Kim , Jong-Ryeol Yoo , Deok-Hyung Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/76
CPC分类号： H01L29/0847 , H01L21/823425 , H01L27/10817 , H01L27/10873 , H01L27/10885 , H01L29/0653 , H01L29/1054 , H01L29/41766 , H01L29/66636 , H01L29/66651 , H01L29/66659
摘要： Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.
摘要翻译：提供了具有这种晶体管的金属氧化物半导体晶体管和器件以及制造这种晶体管和器件的方法。这种晶体管可以具有硅阱区，其具有第一表面并且在其中具有间隔开的源极和漏极区。栅极绝缘体设置在硅阱区的第一表面上并且设置在源极和漏极区之间，并且栅极被设置在栅极绝缘体上。绝缘材料的区域设置在漏极区域的第一表面和硅阱区域之间。绝缘材料的区域朝向但不延伸到源极区域。提供接触源区的源电极。漏电极接触漏极区域和绝缘材料区域。

43. 发明申请

US20080073730A1 Semiconductor device and method for formimg the same 审中-公开
标题翻译：半导体器件和方法相同
公开(公告)号：US20080073730A1
公开(公告)日：2008-03-27
申请号：US11902404
申请日：2007-09-21
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Byeong-Chan Lee , In-Soo Jung
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Byeong-Chan Lee , In-Soo Jung
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/823431 , H01L29/66795
摘要： A method for forming a semiconductor device includes forming at least one gate electrode having a bent structure along a first direction on a semiconductor substrate, the gate electrode having first and second vertical portions, forming at least one semiconductor fin along a second direction on the semiconductor substrate, the semiconductor fin positioned between the first and second vertical portions of the gate electrode, forming a first epitaxial layer on the semiconductor fin, the first epitaxial layer including a source/drain impurity region, and forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a contact impurity region.
摘要翻译：一种形成半导体器件的方法包括：在半导体衬底上沿着第一方向形成具有弯曲结构的至少一个栅电极，所述栅极具有第一和第二垂直部分，在半导体上沿着第二方向形成至少一个半导体鳍片衬底，所述半导体鳍片位于所述栅电极的所述第一和第二垂直部分之间，在所述半导体鳍片上形成第一外延层，所述第一外延层包括源/漏杂质区，以及在所述第一外延层上形成第二外延层层，第二外延层包括接触杂质区。

44. 发明授权

US07385237B2 Fin field effect transistors with low resistance contact structures 有权
标题翻译：具有低电阻接触结构的Fin场效应晶体管
公开(公告)号：US07385237B2
公开(公告)日：2008-06-10
申请号：US11076185
申请日：2005-03-09
申请人： Deok-Hyung Lee , In-Deog Bae , Byeong-Chan Lee , Jong-Wook Lee
发明人： Deok-Hyung Lee , In-Deog Bae , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L29/08
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.
摘要翻译：提供鳍式FET半导体器件，其包括衬底，从衬底垂直突出并且在第一方向上横向延伸的有源图案，具有比活动图案的顶表面低的顶表面的器件隔离层，基板上的栅极结构，其在第二方向上横向延伸以覆盖有源图案的一部分，以及位于与栅极结构的侧部相邻的有源图案的至少部分侧表面上的导电层。导电层可以包括半导体层，并且半导体层可以与接触焊盘电接触。在其它实施例中，导电层可以包括接触垫。

45. 发明申请

US20050199920A1 Fin field effect transistors with low resistance contact structures and methods of manufacturing the same 有权
标题翻译：具有低电阻接触结构的Fin场效应晶体管及其制造方法
公开(公告)号：US20050199920A1
公开(公告)日：2005-09-15
申请号：US11076185
申请日：2005-03-09
申请人： Deok-Hyung Lee , In-Deog Bae , Byeong-Chan Lee , Jong-Wook Lee
发明人： Deok-Hyung Lee , In-Deog Bae , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.
摘要翻译：提供鳍式FET半导体器件，其包括衬底，从衬底垂直突出并且在第一方向上横向延伸的有源图案，具有比活动图案的顶表面低的顶表面的器件隔离层，基板上的栅极结构，其在第二方向上横向延伸以覆盖有源图案的一部分，以及位于与栅极结构的侧部相邻的有源图案的至少部分侧表面上的导电层。导电层可以包括半导体层，并且半导体层可以与接触焊盘电接触。在其它实施例中，导电层可以包括接触垫。

46. 发明授权

US06835996B2 Method and device for forming an STI type isolation in a semiconductor device 失效
标题翻译：在半导体器件中形成STI型隔离的方法和装置
公开(公告)号：US06835996B2
公开(公告)日：2004-12-28
申请号：US10684451
申请日：2003-10-15
申请人： Chul-Sung Kim , Si-Young Choi , Jung-Woo Park , Jong-Ryol Ryu , Byeong-Chan Lee
发明人： Chul-Sung Kim , Si-Young Choi , Jung-Woo Park , Jong-Ryol Ryu , Byeong-Chan Lee
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.
摘要翻译：半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

47. 发明授权

US06660613B2 Method and device for forming an STI type isolation in a semiconductor device 失效
标题翻译：在半导体器件中形成STI型隔离的方法和装置
公开(公告)号：US06660613B2
公开(公告)日：2003-12-09
申请号：US10102997
申请日：2002-03-22
申请人： Chul-Sung Kim , Si-Young Choi , Jung-Woo Park , Jong-Ryol Ryu , Byeong-Chan Lee
发明人： Chul-Sung Kim , Si-Young Choi , Jung-Woo Park , Jong-Ryol Ryu , Byeong-Chan Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.
摘要翻译：半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

48. 发明授权

US06849520B2 Method and device for forming an STI type isolation in a semiconductor device 失效
标题翻译：在半导体器件中形成STI型隔离的方法和装置
公开(公告)号：US06849520B2
公开(公告)日：2005-02-01
申请号：US10685518
申请日：2003-10-16
申请人： Chul-Sung Kim , Si-Young Choi , Jung-Woo Park , Jong-Ryol Ryu , Byeong-Chan Lee
发明人： Chul-Sung Kim , Si-Young Choi , Jung-Woo Park , Jong-Ryol Ryu , Byeong-Chan Lee
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.
摘要翻译：半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

49. 发明授权

US09793356B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US09793356B2
公开(公告)日：2017-10-17
申请号：US14824057
申请日：2015-08-11
申请人： Jeong-Ho Yoo , Byeong-Chan Lee , Hyun-Ho Noh , Yong-Kook Park , Bon-Young Koo , Jin-Yeong Joe
发明人： Jeong-Ho Yoo , Byeong-Chan Lee , Hyun-Ho Noh , Yong-Kook Park , Bon-Young Koo , Jin-Yeong Joe
IPC分类号： H01L29/16 , H01L29/78 , H01L21/8238 , H01L21/84 , H01L29/66 , H01L27/092 , H01L27/12
CPC分类号： H01L29/1608 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant.

50. 发明授权

US08815672B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08815672B2
公开(公告)日：2014-08-26
申请号：US13223783
申请日：2011-09-01
申请人： Seung-Hun Lee , Byeong-Chan Lee , Sang-Bom Kang
发明人： Seung-Hun Lee , Byeong-Chan Lee , Sang-Bom Kang
IPC分类号： H01L21/8238
CPC分类号： H01L27/0922 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/0629 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/7843
摘要： A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.
摘要翻译：一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成第一外延层，以填充第一沟槽。

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