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    • 43. 发明申请
    • OPTICAL SCANNING DEVICE, OPTICAL SCANNING METHOD, PROGRAM, AND IMAGE DISPLAY DEVICE
    • 光学扫描装置,光学扫描方法,程序和图像显示装置
    • US20120275001A1
    • 2012-11-01
    • US13511462
    • 2010-11-09
    • Osamu Ishibashi
    • Osamu Ishibashi
    • G02B26/10
    • G02B26/101H04N9/3129H04N9/3194
    • An optical scanning device includes: a first scanning; a first scanning mirror driving unit; a light emission signal output unit; a light receiving unit; and a phase control unit which controls the first scanning mirror driving unit so as to delay a phase of the oscillation of the first scanning mirror when the light receiving unit outputs the detection signal before intermediate time in a case where the light receiving unit does not output the detection signal during a predetermined period of time, the phase control unit controlling the first scanning mirror driving unit so as to advance a phase of the oscillation of the first scanning mirror when the light receiving unit outputs the detection signal after the intermediate time in the case where the light receiving unit does not output the detection signal during the predetermined period of time.
    • 光学扫描装置包括:第一扫描; 第一扫描镜驱动单元; 发光信号输出单元; 光接收单元; 以及相位控制单元,当在光接收单元不输出的情况下,当光接收单元在中间时间之前输出检测信号时,控制第一扫描镜驱动单元,以便延迟第一扫描镜的振荡的相位 所述检测信号在预定时间段期间,所述相位控制单元控制所述第一扫描镜驱动单元,以便当所述光接收单元在所述第一扫描镜驱动单元中的所述中间时间之后输出所述检测信号时,使所述第一扫描镜的振荡的相位推进 光接收单元在预定时间段内不输出检测信号的情况。
    • 44. 发明授权
    • Data processing apparatus
    • 数据处理装置
    • US08135971B2
    • 2012-03-13
    • US12495991
    • 2009-07-01
    • Sadao MiyazakiOsamu IshibashiRikizo NakanoYoshinori Mesaki
    • Sadao MiyazakiOsamu IshibashiRikizo NakanoYoshinori Mesaki
    • G06F1/00
    • G06F12/0802G06F2212/2024G06F2212/222Y02D10/13
    • A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part.
    • 数据处理装置包括:CPU,包括寄存器,高速缓冲存储器,配置为与高速缓存存储器交换数据的主存储器;被配置为控制主存储器和高速缓冲存储器之间的数据交换的控制部分,以及电源 配置为向寄存器,高速缓冲存储器和主存储器供电的部件。 寄存器,高速缓冲存储器和主存储器都被配置为在不从电源部分提供电力的情况下存储数据并将其保存在其中。 控制部被配置为停止CPU访问在电源部中发生异常的寄存器,高速缓冲存储器和主存储器。
    • 48. 发明授权
    • Data transmission system and method, and electronic apparatus provided with same data transmission system
    • 数据传输系统和方法,以及具有相同数据传输系统的电子设备
    • US07965104B2
    • 2011-06-21
    • US12665763
    • 2008-06-20
    • Osamu Ishibashi
    • Osamu Ishibashi
    • H03K19/0175
    • H04L25/0298
    • A data transmission system includes a transmitter including a drive unit outputting complementary signals to first and second transmission lines according to data for transmission, and a receptor including first and second termination resistors, and a receiver circuit. One ends of the first and second termination resistors are respectively connected to first and second nodes that are connected to first and second transmission lines and other ends of the first and second termination resistors are connected in common to a third node. The receiver circuit supplies a current to the third node and outputs received data corresponding to data for transmission, in accordance with a potential difference between the first and second nodes.
    • 数据传输系统包括发射机,其包括根据用于传输的数据向第一和第二传输线输出互补信号的驱动单元,以及包括第一和第二终端电阻的接收器和接收器电路。 第一和第二终端电阻的一端分别连接到连接到第一和第二传输线的第一和第二节点,并且第一和第二终端电阻的另一端共同连接到第三节点。 根据第一和第二节点之间的电位差,接收器电路向第三节点提供电流并输出与用于传输的数据相对应的接收数据。