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41. 发明授权

US07132852B2 Routing architecture with high speed I/O bypass path 有权
标题翻译：具有高速I / O旁路路径的路由架构
公开(公告)号：US07132852B2
公开(公告)日：2006-11-07
申请号：US10825387
申请日：2004-04-14
申请人： William Bradley Vest , Paul Leventis
发明人： William Bradley Vest , Paul Leventis
IPC分类号： H03K19/173
CPC分类号： H03K19/17792 , H03K19/17736 , H03K19/17744
摘要： Improved routing architectures including one or more high speed input/output (I/O) bypass paths are provided for use in, for example, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). The output bypass paths add additional routing connections to the routing architecture, providing faster connections between the output of a logic element (LE) in the PLD and external circuitry. In one embodiment, an output bypass path is used for directly connecting the output of the LE to the input of an I/O multiplexer of an I/O block. In another embodiment, the output bypass path also bypasses the I/O multiplexer, providing a direct connection between the output of the LE and a bypass multiplexer of the I/O block. Also provided is an input bypass path which provides direct connections between an input buffer of the I/O block and an otherwise dangling conductor at the periphery of the PLD's routing architecture.
摘要翻译：提供了改进的路由架构，包括一个或多个高速输入/输出（I / O）旁路路径，用于例如可编程逻辑器件（PLD），例如现场可编程门阵列（FPGA）。输出旁路路径为路由架构添加了额外的路由连接，从而在PLD中的逻辑元件（LE）的输出与外部电路之间提供更快的连接。在一个实施例中，输出旁路路径用于将LE的输出直接连接到I / O块的I / O多路复用器的输入端。在另一个实施例中，输出旁路路径也绕过I / O多路复用器，提供LE的输出和I / O块的旁路多路复用器之间的直接连接。还提供了一种输入旁路路径，其提供I / O块的输入缓冲器与PLD路由架构外围的另一悬挂导体之间的直接连接。

42. 发明授权

US07084665B1 Distributed random access memory in a programmable logic device 有权
标题翻译：可编程逻辑器件中的分布式随机存取存储器
公开(公告)号：US07084665B1
公开(公告)日：2006-08-01
申请号：US10897743
申请日：2004-07-22
申请人： David Lewis , Paul Leventis , Vaughn Betz
发明人： David Lewis , Paul Leventis , Vaughn Betz
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.
摘要翻译：可编程逻辑器件中的分布式随机存取存储器使用配置RAM位作为分布式RAM的位。单个写入路径用于提供配置数据和用户写入数据。选择电路，例如多路复用器，用于确定单个写入路径是否携带配置数据或用户写入数据。在本发明的另一方面，配置RAM位用于构造移位寄存器，通过添加传输晶体管将配置RAM位链连接在一起，并且以彼此相位180°异相的两个时钟计时交替传输晶体管。

43. 发明授权

US06965249B2 Programmable logic device with redundant circuitry 失效
标题翻译：具有冗余电路的可编程逻辑器件
公开(公告)号：US06965249B2
公开(公告)日：2005-11-15
申请号：US10159581
申请日：2002-05-30
申请人： Christopher Lane , Ketan Zaveri , Hyun Yi , Giles Powell , Paul Leventis , David Jefferson , David Lewis , Triet Nguyen , Vikram Santurkar , Michael Chan , Andy Lee , Brian Johnson , David Cashman
发明人： Christopher Lane , Ketan Zaveri , Hyun Yi , Giles Powell , Paul Leventis , David Jefferson , David Lewis , Triet Nguyen , Vikram Santurkar , Michael Chan , Andy Lee , Brian Johnson , David Cashman
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/17736 , H03K19/17744
摘要： A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.
摘要翻译：可编程逻辑器件和相关方法提供有可修复区域。在一个方面，一般布线互连线在可修复区域内被分段。在另一方面，提供IO总线线路和相关电路，其适应交错分段结构中的冗余。在另一方面，特定逻辑区域之间的专用路由架构适应移位以限定和利用可修复区域。在本发明的方面的几个示例性实施例的上下文中示出和描述了其它方面的原理。

44. 发明申请

US20050127944A1 Versatile logic element and logic array block 有权
公开(公告)号：US20050127944A1
公开(公告)日：2005-06-16
申请号：US11050111
申请日：2005-02-02
申请人： David Lewis , Paul Leventis , Andy Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David Lewis , Paul Leventis , Andy Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

45. 发明授权

US06895570B2 System and method for optimizing routing lines in a programmable logic device 有权
标题翻译：用于优化可编程逻辑器件中路由线路的系统和方法
公开(公告)号：US06895570B2
公开(公告)日：2005-05-17
申请号：US10057232
申请日：2002-01-25
申请人： David M. Lewis , Vaughn Betz , Paul Leventis , Michael Chan , Cameron R. McClintock , Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Richard Cliff
发明人： David M. Lewis , Vaughn Betz , Paul Leventis , Michael Chan , Cameron R. McClintock , Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Richard Cliff
IPC分类号： G06F17/50 , H01L21/82 , H03K19/177
CPC分类号： H03K19/17736 , G06F17/5054 , G06F17/5077
摘要： An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire.A routing architecture is an array that includes rows and columns of function blocks. The columns of the array are connected with horizontal lines (“H-line”) and the rows of the array are connected with vertical lines (“V-line). The types of H-lines include a H4 line that spans four function blocks, a H8 line that spans eight function blocks, and a H24 line that spans twenty-four function blocks. The types of V-lines include a V4 line that spans four function blocks, a V8 line that spans eight function blocks, and a V16 line that spans sixteen function blocks.
摘要翻译：本发明的实施例涉及将可编程逻辑器件（“PLD”）内的多个功能块互连的导线。确定电线最佳物理长度。具有最佳物理长度的导线尽可能快地将信号沿导线传送。在PLD中使用的一些电线具有与电最佳物理长度基本相同的物理长度或电学最佳物理长度的调整以考虑非电学考虑。如本文所使用的物理长度是测量的线的长度。如本文所使用的，线的逻辑长度是导线跨越的功能块的数量。假设功能块具有不同的高度和宽度，则线的逻辑长度根据线的方向而变化。路由架构是包括功能块的行和列的数组。数组的列与水平线（“H-line”）连接，阵列与垂直线（“V线”）连接，H线的类型包括四条功能块的H4线，一个跨越八个功能块的H8线，以及跨越二十四个功能块的H24线，V线的类型包括跨越四个功能块的V4线，跨越八个功能块的V8线，以及V16线线跨越十六个功能块。

46. 发明授权

US06653862B2 Use of dangling partial lines for interfacing in a PLD 有权
公开(公告)号：US06653862B2
公开(公告)日：2003-11-25
申请号：US10140911
申请日：2002-05-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

47. 发明授权

US06630842B1 Routing architecture for a programmable logic device 有权
公开(公告)号：US06630842B1
公开(公告)日：2003-10-07
申请号：US10140287
申请日：2002-05-06
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
IPC分类号： H03K19177
CPC分类号： H03K19/17736
摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides. In this configuration, the width of one of the first channel, the second channel, or the third channel differs from the width of another one of those channels. Input multiplexers route signals from the wires of the channels to the inputs of the function block. Output multiplexers and drivers drive the outputs of the function block through the wires of the channels. By placing the input multiplexers and the output multiplexers in certain relative arrangements, the logical distance that an output signal from the function block can travel on a wire is increased and that signal can be looped back to itself. In addition, each of the inputs and the outputs of the function block can be connected to both horizontal and vertical channels, and an output of the function block can be directly connected to an input of an adjacent function block.

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