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41. 发明申请

US20060187611A1 Method of fabricating MEMS tunable capacitor with wide tuning range 有权
标题翻译：制造具有宽调谐范围的MEMS可调电容器的方法
公开(公告)号：US20060187611A1
公开(公告)日：2006-08-24
申请号：US11408976
申请日：2006-04-24
申请人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
发明人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
IPC分类号： H01G5/00 , H01G7/00
CPC分类号： H01G5/0136 , H01G5/14 , H01G5/145 , H01G5/18
摘要： A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
摘要翻译： MEMS可调谐电容器及其制造方法包括在基板上的多个固定的充电板，多个具有相同高度的固定充电板被布置成梳齿形并彼此电连接，覆盖所述多个固定充电板的电容器电介质层，与所述电容器介电层间隔开并且布置在所述多个固定的充电板上的可移动的充电板结构，其中所述可移动的充电板结构包括多个相应地布置的可移动的充电板多个固定的充电板和连接到可移动的充电板结构的致动器，其允许可移动的充电板结构在水平方向上移动。

42. 发明授权

US08664111B2 Method of patterning a semiconductor device with hard mask 有权
标题翻译：用硬掩模图案化半导体器件的方法
公开(公告)号：US08664111B2
公开(公告)日：2014-03-04
申请号：US13249505
申请日：2011-09-30
申请人： Ha-Jin Lim , Moon-Han Park , Eun-Gon Kim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha-Jin Lim , Moon-Han Park , Eun-Gon Kim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/4763
CPC分类号： H01L21/28123 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/32134 , H01L21/32139 , H01L29/517 , H01L29/518
摘要： There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.
摘要翻译：提供了制造半导体器件的方法。在该方法中，在基板上形成包括高k电介质材料的栅极绝缘层。在栅绝缘层上形成蚀刻停止层。在蚀刻停止层上形成金属层。在金属层上形成包括非晶硅的硬掩模。使用硬掩模作为蚀刻掩模对金属层进行图案化以形成金属层图案。

43. 发明授权

US07435654B2 Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same 有权
标题翻译：具有至少三个高k电介质层的模拟电容器及其制造方法
公开(公告)号：US07435654B2
公开(公告)日：2008-10-14
申请号：US11452828
申请日：2006-06-14
申请人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
发明人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
IPC分类号： H01L21/20 , H01L21/44
CPC分类号： H01L28/40 , H01L21/31637 , H01L21/31645
摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.
摘要翻译：提供了具有至少三个高k电介质层的模拟电容器及其制造方法。模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层为与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

44. 发明申请

US20060234466A1 Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same 有权
标题翻译：具有至少三个高k电介质层的模拟电容器及其制造方法
公开(公告)号：US20060234466A1
公开(公告)日：2006-10-19
申请号：US11452828
申请日：2006-06-14
申请人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
发明人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L21/31637 , H01L21/31645
摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.
摘要翻译：提供了具有至少三个高k电介质层的模拟电容器及其制造方法。模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

45. 发明申请

US20060215348A1 MEMS tunable capacitor with a wide tuning range 有权
标题翻译：具有宽调谐范围的MEMS可调电容器
公开(公告)号：US20060215348A1
公开(公告)日：2006-09-28
申请号：US11444357
申请日：2006-06-01
申请人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
发明人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
IPC分类号： H01G5/00
CPC分类号： H01G5/0136 , H01G5/14 , H01G5/145 , H01G5/18
摘要： A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
摘要翻译： MEMS可调谐电容器及其制造方法包括在基板上的多个固定的充电板，多个具有相同高度的固定充电板被布置成梳齿形并彼此电连接，覆盖所述多个固定充电板的电容器电介质层，与所述电容器介电层间隔开并且布置在所述多个固定的充电板上的可移动的充电板结构，其中所述可移动的充电板结构包括多个相应地布置的可移动的充电板多个固定的充电板和连接到可移动的充电板结构的致动器，其允许可移动的充电板结构在水平方向上移动。

46. 发明授权

US07091548B2 Analog capacitor having at least three high-k-dielectric layers, and method of fabricating the same 有权
标题翻译：具有至少三个高k电介质层的模拟电容器及其制造方法
公开(公告)号：US07091548B2
公开(公告)日：2006-08-15
申请号：US10874461
申请日：2004-06-23
申请人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
发明人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L21/31637 , H01L21/31645
摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.
摘要翻译：提供了具有至少三个高k电介质层的模拟电容器及其制造方法。模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

47. 发明申请

US20050168910A1 MEMS tunable capacitor with a wide tuning range and method of fabricating the same 有权
标题翻译：具有宽调谐范围的MEMS可调电容器及其制造方法
公开(公告)号：US20050168910A1
公开(公告)日：2005-08-04
申请号：US11047762
申请日：2005-02-02
申请人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
发明人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
IPC分类号： H01G5/16 , H01G5/013 , H01G5/14 , H01G5/18 , H01G5/00
CPC分类号： H01G5/0136 , H01G5/14 , H01G5/145 , H01G5/18
摘要： A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
摘要翻译： MEMS可调谐电容器及其制造方法包括在基板上的多个固定的充电板，多个具有相同高度的固定充电板被布置成梳齿形并彼此电连接，覆盖所述多个固定充电板的电容器电介质层，与所述电容器介电层间隔开并且布置在所述多个固定的充电板上的可移动的充电板结构，其中所述可移动的充电板结构包括多个相应地布置的可移动的充电板多个固定的充电板和连接到可移动的充电板结构的致动器，其允许可移动的充电板结构在水平方向上移动。

48. 发明申请

US20050063141A1 Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same 有权
标题翻译：具有至少三个高k电介质层的模拟电容器及其制造方法
公开(公告)号：US20050063141A1
公开(公告)日：2005-03-24
申请号：US10874461
申请日：2004-06-23
申请人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
发明人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
IPC分类号： H01L27/02 , H01G4/20 , H01L21/02 , H01L21/316 , H01L29/00
CPC分类号： H01L28/40 , H01L21/31637 , H01L21/31645
摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.
摘要翻译：提供了具有至少三个高k电介质层的模拟电容器及其制造方法。模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

49. 发明授权

US08476155B1 Formation of a high-K crystalline dielectric composition 有权
标题翻译：形成高K结晶介电组合物
公开(公告)号：US08476155B1
公开(公告)日：2013-07-02
申请号：US12835790
申请日：2010-07-14
申请人： Ha-Jin Lim , Weon-Hong Kim
发明人： Ha-Jin Lim , Weon-Hong Kim
IPC分类号： H01L21/20
CPC分类号： H01L21/02181 , H01L21/02148 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L21/3105 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Provided are a method of forming a dielectric and a method of fabricating a semiconductor device. The method includes forming a preliminary dielectric including Hf, O and an “A” element on an underlying layer. The preliminary dielectric is formed in an amorphous structure or a mixed structure of an amorphous structure and an “M” crystalline structure. The “A” element about 1 at % to about 5 at % of the total content of the “A” element and Hf in the preliminary dielectric. Through a nitridation process, nitrogen is added to the preliminary dielectric. The nitrogen-containing dielectric is changed into a dielectric having a “T” crystalline structure through a phase transition process, wherein the “T” crystalline structure is different from the “M” crystalline structure. An upper layer is formed on the “T” crystalline dielectric.
摘要翻译：提供形成电介质的方法和制造半导体器件的方法。该方法包括在下层上形成包含Hf，O和“A”元素的预备电介质。预置电介质形成为非晶结构或非晶结构和“M”晶体结构的混合结构。 “A”元素在“A”元素的总含量和预置电介质中的Hf的约1at％至约5at％的“A”元素。通过氮化处理，将氮气加入到初步电介质中。通过相变过程将含氮电介质变成具有“T”晶体结构的电介质，其中“T”晶体结构不同于“M”晶体结构。在“T”晶体电介质上形成上层。

50. 发明申请

US20120032332A1 Semiconductor Devices Having A Diffusion Barrier Layer and Methods of Manufacturing the Same 有权
标题翻译：具有扩散阻挡层的半导体器件及其制造方法
公开(公告)号：US20120032332A1
公开(公告)日：2012-02-09
申请号：US13191948
申请日：2011-07-27
申请人： Ha Jin Lim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha Jin Lim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/78 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/4966
摘要： Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.
摘要翻译：制造半导体器件的方法包括在被分成第一区域和第二区域的衬底上形成包括高k电介质材料的栅极绝缘层; 在所述第二区域中的所述栅极绝缘层的第二部分上形成包括第一金属的扩散阻挡层; 在所述栅绝缘层和所述扩散阻挡层上形成扩散层; 以及将所述扩散层的元素扩散到所述第一区域中的所述栅极绝缘层的第一部分中。

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