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41. 发明申请

US20140195822A1 MICROPROCESSOR THAT SECURELY DECRYPTS AND EXECUTES ENCRYPTED INSTRUCTIONS 有权
标题翻译： MICROPROCESSOR THAR SECURYY DECRYPTS AND EXECUTES加密说明
公开(公告)号：US20140195822A1
公开(公告)日：2014-07-10
申请号：US14066428
申请日：2013-10-29
申请人： VIA Technologies, Inc.
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： H04L9/06 , H04L9/08 , G06F21/60
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A microprocessor is provided with a method for decrypting encrypted instruction data into plain text instruction data and securely executing the same. The microprocessor includes a master key register file comprising a plurality of master keys. Selection logic circuitry in the microprocessor selects a combination of at least two of the plurality of master keys. Key expansion circuitry in the microprocessor performs mathematical operations on the selected master keys to generate a decryption key having a long effective key length. Instruction decryption circuitry performs an efficient mathematical operation on the encrypted instruction data and the decryption key to decrypt the encrypted instruction data into plain text instruction data.
摘要翻译：微处理器具有用于将加密指令数据解密为明文指令数据并安全执行该方法。微处理器包括一个包含多个主密钥的主密钥寄存器文件。微处理器中的选择逻辑电路选择多个主密钥中的至少两个的组合。微处理器中的密钥扩展电路对所选择的主密钥执行数学运算，以产生具有长的有效密钥长度的解密密钥。指令解密电路对加密指令数据和解密密钥进行有效的数学运算，将加密指令数据解密为明文指令数据。

42. 发明申请

US20140195821A1 METHOD FOR ENCRYPTING A PROGRAM FOR SUBSEQUENT EXECUTION BY A MICROPROCESSOR CONFIGURED TO DECRYPT AND EXECUTE THE ENCRYPTED PROGRAM 有权
标题翻译：加密程序用于后续执行的程序，由配置为解密并执行加密程序的微处理器
公开(公告)号：US20140195821A1
公开(公告)日：2014-07-10
申请号：US14066350
申请日：2013-10-29
申请人： VIA Technologies, Inc.
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/60
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program includes receiving an object file specifying an unencrypted program that includes conventional branch instructions whose target address may be determined pre-run time. The method also includes analyzing the program to obtain chunk information that divides the program into a sequence of chunks each comprising a sequence of instructions and that includes encryption key data associated with each of the chunks. The encryption key data associated with each of the chunks is distinct. The method also includes replacing each of the conventional branch instructions that specifies a target address that is within a different chunk than the chunk in which the conventional branch instruction resides with a branch and switch key instruction. The method also includes encrypting the program based on the chunk information.
摘要翻译：用于加密被配置为解密和执行加密程序的微处理器后续执行的程序的方法包括接收指定未加密程序的目标文件，其包括其目标地址可以被确定为预先运行时间的常规分支指令。该方法还包括分析程序以获得将程序划分成每个包括指令序列并且包括与每个块相关联的加密密钥数据的块的序列的块信息。与每个块相关联的加密密钥数据是不同的。该方法还包括用分支和切换键指令代替指定与常规分支指令所在的块不同的块内的目标地址的每个常规分支指令。该方法还包括基于块信息来加密程序。

43. 发明申请

US20140195820A1 APPARATUS FOR GENERATING A DECRYPTION KEY FOR USE TO DECRYPT A BLOCK OF ENCRYPTED INSTRUCTION DATA BEING FETCHED FROM AN INSTRUCTION CACHE IN A MICROPROCESSOR 有权
标题翻译：用于生成用于解密加密指令数据的块的装置用于从微处理器中的指令高速缓冲存储器
公开(公告)号：US20140195820A1
公开(公告)日：2014-07-10
申请号：US14066270
申请日：2013-10-29
申请人： VIA Technologies, Inc.
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： H04L9/08 , G06F12/08
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： An apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor at a fetch address includes a first multiplexer that selects a first key value from a plurality of key values based on a first portion of the fetch address. A second multiplexer selects a second key value from the plurality of key values based on the first portion of the fetch address. A rotater rotates the first key value based on a second portion of the fetch address. An arithmetic unit selectively adds or subtracts the rotated first key value to or from the second key value based on a third portion of the fetch address to generate the decryption key.
摘要翻译：一种用于产生解密密钥的装置，用于解密从提取地址的微处理器中的指令高速缓存取出的加密指令数据块，其包括：第一多路复用器，其基于第一和第二多个键值从多个键值中选择第一键值提取地址的一部分。第二多路复用器根据提取地址的第一部分从多个键值中选择第二键值。旋转器基于获取地址的第二部分旋转第一键值。算术单元基于获取地址的第三部分，有选择地向第二密钥值添加或减去所转动的第一密钥值，以生成解密密钥。

44. 发明申请

US20130311755A1 RUNNING STATE POWER SAVING VIA REDUCED INSTRUCTIONS PER CLOCK OPERATION 有权
标题翻译：每个时钟运行通过减少的指令节省运行状态
公开(公告)号：US20130311755A1
公开(公告)日：2013-11-21
申请号：US13777104
申请日：2013-02-26
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/329 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/24
摘要： A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states.
摘要翻译：微处理器包括可写的功能单元和控制寄存器，以使功能单元执行动作，以减少微处理器的每时钟指令的指令，以在微处理器以最低性能运行状态运行时降低功耗。这些操作的示例包括按顺序执行，无序执行，串行与并行缓存访问以及每个时钟周期中的单个或多个指令发出，退出，转换和/或格式化。只有在存在附加条件的情况下，才能设置动作，例如最低运行时间停留在最低运行状态，不超过最长时间运行在较高的运行状态，用户没有禁用该功能，微处理器支持多个运行状态和操作系统支持多个运行状态。

45. 发明授权

US10175732B2 Domain-differentiated power state coordination system 有权
公开(公告)号：US10175732B2
公开(公告)日：2019-01-08
申请号：US14980194
申请日：2015-12-28
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Darius D. Gaskins
IPC分类号： G06F1/26 , G06F1/32 , G06F1/24 , G06F13/36 , G06F15/163 , G06F9/30 , G06F9/50 , G06F9/445 , G06F15/82 , G06F11/36 , G06F11/14
摘要： A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

46. 发明授权

US10108431B2 Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state 有权
公开(公告)号：US10108431B2
公开(公告)日：2018-10-23
申请号：US15265127
申请日：2016-09-14
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Stephan Gaskins
IPC分类号： G06F1/00 , G06F9/38 , G06F1/32 , G06F12/084 , G06F13/24 , G06F9/4401 , G06F13/364 , G06F12/0808 , G06F9/30 , G06F12/0875 , G06F1/04 , G06F1/12 , G06F13/42 , G06F21/53 , G06F21/57 , H04L9/08 , H01L21/66
摘要： A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

47. 发明授权

US10089470B2 Event-based apparatus and method for securing BIOS in a trusted computing system during execution 有权
公开(公告)号：US10089470B2
公开(公告)日：2018-10-02
申请号：US15380706
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry
IPC分类号： G06F21/57 , G06F9/44 , G06F21/55 , G06F9/4401 , G06F13/24 , G06F13/42 , H04L9/32 , H04L29/06 , H04L9/06 , H04L9/08
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a change in system state. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

48. 发明授权

US10055588B2 Event-based apparatus and method for securing BIOS in a trusted computing system during execution 有权
公开(公告)号：US10055588B2
公开(公告)日：2018-08-21
申请号：US15380825
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry
IPC分类号： G06F21/57 , G06F21/55 , H04L9/32
CPC分类号： G06F21/572 , G06F21/554 , G06F2221/2107 , H04L9/3242
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a power glitch exceeding a specified threshold within a specified time period. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

49. 发明授权

US09967092B2 Key expansion logic using decryption key primitives 有权
公开(公告)号：US09967092B2
公开(公告)日：2018-05-08
申请号：US14884416
申请日：2015-10-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： H04L29/06 , H04L9/08 , G06F12/14 , G06F12/0862 , G06F12/0855 , G06F12/0875 , G06F9/30 , G06F21/52 , G06F21/54 , G06F21/60 , G06F21/71 , G06F21/72 , H04L9/06
CPC分类号： H04L9/0825 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0855 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/6026 , G06F2221/2107 , H04L9/0618 , H04L9/0827 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A secure memory, key expansion logic, and decryption logic are provided for a microprocessor that executes encrypted instructions. The secure memory stores a plurality of decryption key primitives. The key expansion logic selects two or more decryption key primitives from the secure memory and then derives a decryption key from them. The decryption logic uses the decryption key to decrypt an encrypted instruction fetched from the instruction cache. The decryption key primitives are selected on the basis of an encrypted instruction address, one of them is rotated by an amount also determined by the encrypted instruction address, and then they are additively or subtractively accumulated, also on the basis of the encrypted instruction address.

50. 发明授权

US09952654B2 Centralized synchronization mechanism for a multi-core processor 有权
公开(公告)号：US09952654B2
公开(公告)日：2018-04-24
申请号：US14994544
申请日：2016-01-13
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F1/32 , G06F9/52 , G06F1/04 , G06F12/0891
CPC分类号： G06F1/3287 , G06F1/04 , G06F1/32 , G06F9/522 , G06F12/0891 , G06F2212/1028 , G06F2212/60
摘要： A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core's target operating state.

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