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    • 42. 发明申请
    • PROVIDING LOGICAL PARTIONS WITH HARDWARE-THREAD SPECIFIC INFORMATION REFLECTIVE OF EXCLUSIVE USE OF A PROCESSOR CORE
    • 提供具有硬件特征信息的逻辑分段反映处理器核心的独家使用
    • US20130179886A1
    • 2013-07-11
    • US13452745
    • 2012-04-20
    • Giles R. FrazierBruce MealyNaresh Nayar
    • Giles R. FrazierBruce MealyNaresh Nayar
    • G06F9/46
    • G06F21/6218G06F9/3012G06F9/3851G06F9/45541G06F9/45558G06F2009/45587
    • Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
    • 用于模拟在多个逻辑分区(LPAR)中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息,所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器 信息。 如果请求者是在低于管理程序权限级别的特权级别下执行的程序,则转换响应于访问请求而返回的信息,使得每个逻辑分区将处理器视为处理器的独占使用。 这些技术可以由处理器核心内的逻辑电路块来实现,其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示,或者可以通过将访问陷阱的中断处理程序的程序指令执行 物理寄存器包含信息。
    • 43. 发明授权
    • Transparently increasing power savings in a power management environment
    • 在电源管理环境中透明地增加功耗
    • US08423811B2
    • 2013-04-16
    • US13457030
    • 2012-04-26
    • Naresh NayarKarthik RajamaniFreeman L. Rawson, III
    • Naresh NayarKarthik RajamaniFreeman L. Rawson, III
    • G06F1/00
    • G06F1/3203G06F9/5077G06F9/5094Y02D10/22Y02D10/36
    • A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode.
    • 提供了一种用于透明地整合逻辑分区资源的机制。 响应于原始资源芯片上的非折叠资源的存在,虚拟化机制确定是否存在目的地资源芯片,以在目的地芯片上用折叠资源来交换非折叠资源的操作,或者迁移操作 非折叠资源到目标芯片上的非折叠资源。 响应于目标资源芯片上折叠资源的存在,虚拟化机制透明地将未折叠资源的操作从始发资源芯片交换到目的地资源芯片上的折叠资源,其中折叠资源保持折叠在 交换后的源资源芯片。 响应于起始资源芯片上不存在另一非折叠资源,激活机制将始发资源芯片置于更深的省电模式。
    • 44. 发明申请
    • PRIVILEGE LEVEL AWARE PROCESSOR HARDWARE RESOURCE MANAGEMENT FACILITY
    • 特权级注意处理器硬件资源管理设施
    • US20130086581A1
    • 2013-04-04
    • US13251879
    • 2011-10-03
    • Giles R. FrazierMichael K. GschwindNaresh Nayar
    • Giles R. FrazierMichael K. GschwindNaresh Nayar
    • G06F9/455
    • G06F9/45533G06F9/45558G06F9/462G06F9/5077G06F2009/45579
    • Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.
    • 多个机器状态寄存器被包括在处理器核心中,以便区分应用程序,监督线程和管理程序之间的硬件设施的使用。 当初始化分区时,所有的设备最初被管理程序禁用。 当对残疾设施进行访问时,管理程序将收到访问哪个设施的指示,并在管理程序的机器状态寄存器中设置相应的硬件标志。 当应用程序尝试访问禁用的设备时,管理操作系统映像的主管接收到哪个设备被访问的指示,并在主管机器状态寄存器中设置相应的硬件标志。 多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态,并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。