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41. 发明申请

US20060154425A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060154425A1
公开(公告)日：2006-07-13
申请号：US11032439
申请日：2005-01-10
申请人： Ming-Ho Yang , Karen Mai , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Ho Yang , Karen Mai , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28061 , H01L21/28194 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device and method for fabricating the same. The semiconductor device comprises a substrate with a gate stack thereon, wherein the gate stack comprises a high-k dielectric layer and a conductive layer sequentially overlying a portion of the substrate. An oxidation-proof layer overlies sidewalls of the gate stack. A pair of insulating spacers oppositely overlies sidewalls of the gate stack and the oxidation-proof layers thereon and a pair of source/drain regions is oppositely formed in the substrate adjacent to the gate stack, wherein the oxidation-proof layer suppresses oxidation encroachment between the gate stack and the substrate.
摘要翻译：一种半导体器件及其制造方法。半导体器件包括其上具有栅极堆叠的衬底，其中栅极堆叠包括高k电介质层和顺序地覆盖衬底的一部分的导电层。防氧化层覆盖在栅叠层的侧壁上。一对绝缘隔片相对地覆盖在栅堆叠的侧壁和其上的防氧化层上，并且一对源极/漏极区域相邻地形成在与栅极叠层相邻的衬底中，其中防氧化层抑制了栅极叠层之间的氧化侵蚀栅极堆叠和衬底。

42. 发明授权

US06982208B2 Method for producing high throughput strained-Si channel MOSFETS 失效
标题翻译：生产高通量应变Si沟道MOSFET的方法
公开(公告)号：US06982208B2
公开(公告)日：2006-01-03
申请号：US10838625
申请日：2004-05-03
申请人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
发明人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/30
CPC分类号： H01L21/02505 , C30B25/02 , C30B29/52 , H01L21/02052 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/7842
摘要： A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.
摘要翻译：一种用于形成具有改善的晶片生产量和低缺陷密度的应变硅层器件的方法，包括提供硅衬底; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长第一硅层; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长阶梯级SiGe缓冲层并使第一硅层接触; 使用至少一种选自乙硅烷和丙硅烷的沉积前体外延生长SiGe覆盖层并使其与阶级SiGe缓冲层接触; 以及使用至少一种选自乙硅烷和硅烷的沉积前体外延生长第二硅层。

43. 发明授权

US07592619B2 Epitaxy layer and method of forming the same 有权
标题翻译：外延层及其形成方法
公开(公告)号：US07592619B2
公开(公告)日：2009-09-22
申请号：US11622490
申请日：2007-01-12
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： H01L29/15
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

44. 发明授权

US07357838B2 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US07357838B2
公开(公告)日：2008-04-15
申请号：US11074738
申请日：2005-03-08
申请人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B23/00
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided.
摘要翻译：提供了在松弛的低缺陷密度半导体合金层（例如SiGe）上形成应变硅层的方法。

45. 发明授权

US07175709B2 Epitaxy layer and method of forming the same 有权
标题翻译：外延层及其形成方法
公开(公告)号：US07175709B2
公开(公告)日：2007-02-13
申请号：US10847099
申请日：2004-05-17
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： C30B25/04
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

46. 发明申请

US20050245058A1 METHOD FOR PRODUCING HIGH THROUGHPUT STRAINED-SI CHANNEL MOSFETS 失效
标题翻译：用于生产高通量应变SI沟道MOSFET的方法
公开(公告)号：US20050245058A1
公开(公告)日：2005-11-03
申请号：US10838625
申请日：2004-05-03
申请人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
发明人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
IPC分类号： C30B1/00 , C30B25/02 , H01L21/20 , H01L21/205 , H01L21/306 , H01L21/36 , H01L21/44
CPC分类号： H01L21/02505 , C30B25/02 , C30B29/52 , H01L21/02052 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/7842
摘要： A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.
摘要翻译：一种用于形成具有改善的晶片生产量和低缺陷密度的应变硅层器件的方法，包括提供硅衬底; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长第一硅层; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长阶梯级SiGe缓冲层并使第一硅层接触; 使用至少一种选自乙硅烷和丙硅烷的沉积前体外延生长SiGe覆盖层并使其与阶级SiGe缓冲层接触; 以及使用至少一种选自乙硅烷和硅烷的沉积前体外延生长第二硅层。

47. 发明授权

US06936530B1 Deposition method for Si-Ge epi layer on different intermediate substrates 有权
标题翻译：不同中间基板上Si-Ge外延层的沉积方法
公开(公告)号：US06936530B1
公开(公告)日：2005-08-30
申请号：US10772939
申请日：2004-02-05
申请人： Liang-Gi Yao , Kuen-Chyr Lee , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Kuen-Chyr Lee , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/331
CPC分类号： H01L29/66242 , H01L21/02532 , H01L21/02579 , H01L21/0262 , Y10S438/918
摘要： A method of forming an Si—Ge epitaxial layer comprising the following steps. A structure is provided and a doped Si—Ge seed layer is formed thereover. The doped Si—Ge seed layer having increased nucleation sites. A Si—Ge epitaxial layer upon the doped Si—Ge seed layer whereby the Si—Ge epitaxial layer lacks discontinuity.
摘要翻译：一种形成Si-Ge外延层的方法，包括以下步骤。提供一种结构，并在其上形成掺杂的Si-Ge种子层。掺杂的Si-Ge种子层具有增加的成核位点。在掺杂Si-Ge晶种层上的Si-Ge外延层，由此Si-Ge外延层缺少不连续性。

48. 发明授权

US06861339B2 Method for fabricating laminated silicon gate electrode 有权
标题翻译：叠层硅栅电极的制造方法
公开(公告)号：US06861339B2
公开(公告)日：2005-03-01
申请号：US10274570
申请日：2002-10-21
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/20 , H01L21/28 , H01L21/30 , H01L29/49 , H01L29/78 , H01L21/26
CPC分类号： H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/28035 , H01L21/3003 , H01L29/4925 , H01L29/78
摘要： Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.
摘要翻译：在形成硅层的方法中，使用由较高结晶硅材料形成的至少一个子层和由下部结晶硅材料形成的至少一个子层。使用较高结晶硅材料的氢处理形成下部结晶硅材料。该方法对于形成具有增强尺寸控制和增强性能的多晶硅基栅电极特别有用。

49. 发明授权

US06780741B2 Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers 失效
标题翻译：形成由位于无规晶粒多晶硅层之间的硅 - 锗层构成的新型栅电极结构的方法
公开(公告)号：US06780741B2
公开(公告)日：2004-08-24
申请号：US10338155
申请日：2003-01-08
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L213205
CPC分类号： H01L21/28044 , H01L29/4925
摘要： A method of fabricating a gate structure for a MOSFET device, allowing a reduced polysilicon depletion effect as well as increased carrier mobility to be realized, has been developed. The method features a polysilicon-germanium component of the gate structure, sandwiched between an underlying polysilicon seed layer and an overlying polysilicon cap layer. The inclusion of germanium in the deposited polysilicon-germanium component results in enhanced dopant activation and thus a reduced polysilicon depletion effect. The polysilicon seed and cap layers are subjected to low temperature, anneal procedures, performed in situ in a hydrogen ambient, after deposition of the polysilicon layers. The in situ anneal procedures alters the columnar grains of the polysilicon layers to small, random grains resulting in smooth polysilicon surfaces, with the smooth surface of the polysilicon seed layer interfacing the underlying gate insulator layer resulting in enhanced carrier mobility when compared to counterpart polysilicon seed layer comprised with rough surfaces.
摘要翻译：已经开发了制造用于MOSFET器件的栅极结构的方法，其允许减少的多晶硅耗尽效应以及增加的载流子迁移率被实现。该方法具有栅极结构的多晶硅 - 锗组分，夹在下面的多晶硅种子层和上覆多晶硅覆盖层之间。在沉积的多晶硅 - 锗组分中包含锗导致增强的掺杂剂活化，从而减少了多晶硅的耗尽效应。多晶硅种子和盖层经过低温退火处理，在沉积多晶硅层之后在氢环境中原位进行。原位退火程序将多晶硅层的柱状晶体改变成小的随机晶粒，产生平滑的多晶硅表面，与对应的多晶硅晶粒相比，多晶硅籽晶层的平滑表面与下面的栅极绝缘体层相接触，导致增强的载流子迁移率层包含粗糙表面。

50. 发明授权

US07229919B2 Semiconductor device having a random grained polysilicon layer and a method for its manufacture 有权
标题翻译：具有随机晶粒多晶硅层的半导体器件及其制造方法
公开(公告)号：US07229919B2
公开(公告)日：2007-06-12
申请号：US10870878
申请日：2004-06-17
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/44
CPC分类号： H01L21/28044 , C23C16/24 , H01L21/0245 , H01L21/02532 , H01L21/02595 , H01L21/02609 , H01L21/0262 , H01L21/28052 , H01L29/4925
摘要： A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.
摘要翻译：提供了具有随机晶粒多晶硅层的半导体器件及其制造方法。在一个示例中，该器件在衬底上包括半导体衬底和绝缘体层。具有随机晶粒结构的第一多晶硅层位于绝缘体层的上方，半导体合金层位于第一多晶硅层的上方，第二多晶硅层位于半导体合金层的上方。

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