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41. 发明授权

US5874777A Semiconductor device with enhanced thermal conductivity 失效
标题翻译：具有增强导热性的半导体器件
公开(公告)号：US5874777A
公开(公告)日：1999-02-23
申请号：US716191
申请日：1996-12-02
申请人： Tadahiro Ohmi , Kazuo Tsubouchi , Toshiyuki Takewaki
发明人： Tadahiro Ohmi , Kazuo Tsubouchi , Toshiyuki Takewaki
IPC分类号： H01L21/28 , H01L21/285 , H01L21/312 , H01L21/314 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76801 , H01L23/5222 , H01L23/5226 , H01L2924/0002 , H01L2924/12044
摘要： There is provided a semiconductor device high in speed and in reliability by formation of interlayer dielectric films capable of rapidly transmitting heat as generated at wiring lines and yet less in capacitance.The semiconductor device of the present invention has multi-layered low-resistance wiring lines such as metal layers as stacked or laminated on a top surface and/or a bottom surface of a conductive substrate with a first dielectric material being sandwiched between adjacent ones thereof, featured in that said first dielectric material between said low-resistance wiring layers has a through-hole formed therein, and that said through-hole comprises a hole (through-hole: TH) filled with at least a conductive material, and a hole (dummy hole; DH) filed with a second dielectric material having thermal conductivity greater than that of said first dielectric material. Furthermorer the device is featured by having similar TH and DH between said low-resistance wiring lines and said conductive substrate, or between a specific low-resistance wiring line positioned at the uppermost layer of said low-resistance wiring lines and a heat release device also.
摘要翻译： PCT No.PCT / JP96 / 00165 Sec。 371日期1996年12月2日第 102（e）日期1996年12月2日PCT提交1996年1月29日PCT公布。公开号WO96 / 24159 日期1996年8月8日通过形成能够快速传输在布线上产生的热量并且电容较小的层间电介质膜，提供了高速度和可靠性的半导体器件。本发明的半导体装置具有在导电性基板的顶面和/或底面层叠或层叠金属层的多层低电阻布线，其中第一介电材料夹在其相邻之间，特征在于，所述低电阻布线层之间的所述第一介电材料具有形成在其中的通孔，并且所述通孔包括填充有至少导电材料的孔（通孔：TH）和孔（虚拟孔; DH）提供具有大于所述第一介电材料的热导率的第二介电材料。此外，该装置的特征在于在所述低电阻布线和所述导电基板之间或位于位于所述低电阻布线的最上层的特定低电阻布线之间具有类似的TH和DH以及散热装置。

42. 发明授权

US07821101B2 Semiconductor device including capacitor including upper electrode covered with high density insulation film and production method thereof 失效
标题翻译：包括具有覆盖有高密度绝缘膜的上电极的电容器的半导体装置及其制造方法
公开(公告)号：US07821101B2
公开(公告)日：2010-10-26
申请号：US12081194
申请日：2008-04-11
申请人： Toshiyuki Takewaki , Daisuke Oshida , Takuji Onuma
发明人： Toshiyuki Takewaki , Daisuke Oshida , Takuji Onuma
IPC分类号： H01L29/92
CPC分类号： H01L28/40
摘要： A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with an upper part of the upper electrode and on the upper part of the lower electrode, and having a density higher than that of the first insulating film, the second insulating film covering a side surface and a top surface of the upper electrode.
摘要翻译：半导体器件包括设置在半导体衬底上的下电极，设置在下电极上以与下电极的一部分重叠的上电极，设置在下电极和上电极之间的第一绝缘膜和设置在下电极和上电极之间的第二绝缘膜与上电极的上部和下电极的上部接触，并且具有比第一绝缘膜高的密度，第二绝缘膜覆盖上电极的侧表面和顶表面。

43. 发明授权

US07601640B2 Method of manfacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07601640B2
公开(公告)日：2009-10-13
申请号：US11953127
申请日：2007-12-10
申请人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
发明人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
IPC分类号： H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译：如下进行铜层的CMP后清洗工序。依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。

44. 发明申请

US20090184421A1 SEMICONDUCTOR DEVICE WITH HIGH RELIABILITY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有高可靠性和制造方法的半导体器件
公开(公告)号：US20090184421A1
公开(公告)日：2009-07-23
申请号：US12350448
申请日：2009-01-08
申请人： Daisuke Oshida , Toshiyuki Takewaki , Shinji Yokogawa
发明人： Daisuke Oshida , Toshiyuki Takewaki , Shinji Yokogawa
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76865 , H01L21/76873 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.
摘要翻译：提供了一种半导体器件，其包括衬底，在衬底上形成的绝缘膜，以及包含铜作为主要成分的不同宽度的多个金属配线和不同于铜的杂质。多个金属布线包括具有浓度分布的第一金属布线，其中杂质金属的浓度从堆叠方向的中心部分增加到表面，第二金属布线具有浓度分布，其中杂质金属的浓度从底面向堆叠方向的表面。此外，第二金属布线的宽度可以大于第一金属布线的宽度。

45. 发明授权

US07514352B2 Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases 有权
标题翻译：具有随着宽度增加而杂质浓度增加的互连结构的半导体器件的制造方法
公开(公告)号：US07514352B2
公开(公告)日：2009-04-07
申请号：US11892707
申请日：2007-08-27
申请人： Toshiyuki Takewaki
发明人： Toshiyuki Takewaki
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/5283 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.
摘要翻译：本发明提供能够抑制窄互连的电阻的增加同时保持宽互连的可靠性降低的半导体器件。半导体器件包括多个互连层，并且多个互连层中的至少一个互连层中的互连包含杂质，并且所述至少一个互连层中的互连越宽，杂质浓度越高互连包含。

46. 发明申请

US20080237793A1 Semiconductor device having projection on lower electrode and method for forming the same 失效
标题翻译：具有在下电极上的投影的半导体器件及其形成方法
公开(公告)号：US20080237793A1
公开(公告)日：2008-10-02
申请号：US12073545
申请日：2008-03-06
申请人： Daisuke Oshida , Toshiyuki Takewaki , Takuji Onuma , Koichi Ohto
发明人： Daisuke Oshida , Toshiyuki Takewaki , Takuji Onuma , Koichi Ohto
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L28/84
摘要： A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底上形成包括金属和氮的下电极，将还原气体照射到下电极的表面，并将含硅的气体照射到下电极的表面，以通过在下电极的表面上使金属与岛状的硅反应形成包含硅化物的突起。然后，在下电极和突起上形成电容器膜，并且在电容器膜上形成上电极。

47. 发明申请

US20080064202A1 Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases 有权
标题翻译：具有随着宽度增加而杂质浓度增加的互连结构的半导体器件的制造方法
公开(公告)号：US20080064202A1
公开(公告)日：2008-03-13
申请号：US11892707
申请日：2007-08-27
申请人： Toshiyuki Takewaki
发明人： Toshiyuki Takewaki
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/5283 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.
摘要翻译：本发明提供能够抑制窄互连的电阻的增加同时保持宽互连的可靠性降低的半导体器件。半导体器件包括多个互连层，并且多个互连层中的至少一个互连层中的互连包含杂质，并且所述至少一个互连层中的互连越宽，杂质浓度越高互连包含。

48. 发明授权

US07274104B2 Semiconductor device having an interconnect that increases in impurity concentration as width increases 有权
标题翻译：具有随着宽度增加而杂质浓度增加的互连的半导体器件
公开(公告)号：US07274104B2
公开(公告)日：2007-09-25
申请号：US10994479
申请日：2004-11-23
申请人： Toshiyuki Takewaki
发明人： Toshiyuki Takewaki
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/5283 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.
摘要翻译：本发明提供能够抑制窄互连的电阻的增加同时保持宽互连的可靠性降低的半导体器件。半导体器件包括多个互连层，并且多个互连层中的至少一个互连层中的互连包含杂质，并且所述至少一个互连层中的互连越宽，杂质浓度越高互连包含。

49. 发明申请

US20070034924A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070034924A1
公开(公告)日：2007-02-15
申请号：US11502429
申请日：2006-08-11
申请人： Toshiyuki Takewaki , Takeshi Toda
发明人： Toshiyuki Takewaki , Takeshi Toda
IPC分类号： H01L29/94
CPC分类号： H01L23/5223 , H01L21/7684 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device 1 includes an insulating interlayer 10, interconnects 12a to 12c, an insulating interlayer 20, and a capacitor element 30. On the insulating interlayer 10 and the interconnects 12a to 12d, the insulating interlayer 20 is provided via a diffusion barrier 40. On the insulating interlayer 20, the capacitor element 30 is provided. The capacitor element 30 is a MIM type capacitor element, and includes a lower electrode 32 provided on the insulating interlayer 20, a capacitor insulating layer 34 provided on the lower electrode 32, and an upper electrode 36 provided on the capacitor insulating layer 34. The interface S1 between the insulating interlayer 20 and the capacitor element 30 is generally flat. The lower face S2 of the insulating interlayer 20 includes an uneven portion at a position corresponding to the capacitor insulating layer 34.
摘要翻译：半导体器件1包括绝缘中间层10，互连12a至12c，绝缘中间层20和电容器元件30.在绝缘中间层10和互连12 a至12 d上，绝缘中间层20经由在绝缘中间层20上设置电容器元件30。电容器元件30是MIM型电容器元件，并且包括设置在绝缘中间层20上的下电极32，设置在下电极32上的电容器绝缘层34和设置在电容器绝缘层34上的上电极36。绝缘中间层20和电容器元件30之间的界面S1一般为平坦的。绝缘夹层20的下表面S 2在与电容器绝缘层34对应的位置处具有凹凸部。

50. 发明授权

US07052994B2 Method for manufacturing semiconductor device, and processing system and semiconductor device 有权
标题翻译：制造半导体器件的方法，以及处理系统和半导体器件
公开(公告)号：US07052994B2
公开(公告)日：2006-05-30
申请号：US09840386
申请日：2001-04-23
申请人： Yoshihisa Matsubara , Toshiyuki Takewaki , Manabu Iguchi
发明人： Yoshihisa Matsubara , Toshiyuki Takewaki , Manabu Iguchi
IPC分类号： H01L21/302
CPC分类号： H01L21/67028 , H01L21/76838
摘要： A method for manufacturing a semiconductor device comprises: forming an N region and P region on a substrate, forming wiring so as to connect one or both of these N and P regions; and performing a processing step on a semiconductor substrate on which the upper surface of said wiring is exposed using a liquid, wherein said processing step is performed in a state in which the wavelength of light radiated onto said semiconductor substrate is 500 nm to less than 1 μm, so that problems such as wiring connection defects for which there is the risk of occurring in the cleaning step are prevented by performing the cleaning step during, before or after a step that includes chemical mechanical polishing (CMP) for forming the above wiring.
摘要翻译：一种制造半导体器件的方法包括：在衬底上形成N区和P区，形成布线以连接这些N和P区中的一个或两个; 以及使用液体在所述布线的上表面露出的半导体衬底上进行处理步骤，其中所述处理步骤是在辐射到所述半导体衬底上的光的波长为500nm至小于1的状态下进行的因此通过在包括用于形成上述布线的化学机械抛光（CMP）的步骤之前，之后执行清洁步骤来防止在清洁步骤中存在发生危险的诸如布线连接缺陷的问题。

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