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41. 发明授权

US08598649B2 Nonvolatile semiconductor memory device and method for manufacturing same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08598649B2
公开(公告)日：2013-12-03
申请号：US12792378
申请日：2010-06-02
申请人： Takayuki Okamura , Noboru Ooike , Wataru Sakamoto , Takashi Izumida
发明人： Takayuki Okamura , Noboru Ooike , Wataru Sakamoto , Takashi Izumida
IPC分类号： H01L29/792 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11565 , H01L21/28282 , H01L27/11568
摘要： A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.
摘要翻译：根据实施例的非易失性半导体存储器件包括：半导体衬底，其具有被分隔成沿第一方向延伸的多个半导体部分的上部; 设置在半导体部分上的电荷存储膜; 字线电极，其设置在所述半导体基板上并沿与所述第一方向交叉的第二方向延伸; 以及一对选择栅电极，其设置在所述半导体基板上的所述字线电极的所述第一方向的两侧，并且沿所述第二方向延伸，所述半导体部分的每个的角部与所述选择中的每一个之间的最短距离栅电极比与半导体部分的角部和字线电极之间的平行于第二方向的截面中的最短距离更长。

42. 发明申请

US20120146128A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120146128A1
公开(公告)日：2012-06-14
申请号：US13364588
申请日：2012-02-02
申请人： Takashi Izumida , Nobutoshi Aoki
发明人： Takashi Izumida , Nobutoshi Aoki
IPC分类号： H01L27/088
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/0688 , H01L27/11578 , H01L27/11582
摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.
摘要翻译：在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。第二硅化物具有与第一硅化物相同的组成。第二宽度大于第一宽度。

43. 发明申请

US20120003801A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120003801A1
公开(公告)日：2012-01-05
申请号：US13224449
申请日：2011-09-02
申请人： Takashi Izumida , Nobutoshi Aoki
发明人： Takashi Izumida , Nobutoshi Aoki
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/1054 , H01L29/66795
摘要： A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.
摘要翻译：半导体器件具有半导体衬底，形成在半导体衬底上的具有长边方向和短边方向的半导体鳍片，并且具有包含杂质的含碳硅膜和形成在其上的硅膜含碳硅膜，形成为在短边方向上面对半导体翅片的两侧面的栅电极，分别形成在长边方向两侧的半导体翅片中的源区和漏区半导体鳍片的方向以夹着栅极电极;以及元件隔离绝缘膜，其形成在半导体鳍片的侧表面上以及栅电极和半导体衬底之间。

44. 发明授权

US08043904B2 Semiconductor manufacturing method and semiconductor device 有权
标题翻译：半导体制造方法和半导体器件
公开(公告)号：US08043904B2
公开(公告)日：2011-10-25
申请号：US12613143
申请日：2009-11-05
申请人： Takashi Izumida , Sanae Ito , Takahisa Kanemura
发明人： Takashi Izumida , Sanae Ito , Takahisa Kanemura
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78609
摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
摘要翻译：制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

45. 发明申请

US20110068401A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110068401A1
公开(公告)日：2011-03-24
申请号：US12881415
申请日：2010-09-14
申请人： Takashi Izumida , Nobutoshi Aoki , Masaki Kondo , Yoshiaki Asao , Satoshi Inaba
发明人： Takashi Izumida , Nobutoshi Aoki , Masaki Kondo , Yoshiaki Asao , Satoshi Inaba
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： A semiconductor device of an embodiment includes a substrate and a plurality of fins formed on the substrate. The plurality of fins is arranged so that a first distance and a second distance narrower than the first distance are repeated. In addition, the plurality of fins include a semiconductor region in which an impurity concentration of lower portions of side surfaces facing each other in sides forming the first distance is higher than an impurity concentration of lower portions of side surfaces facing each other in sides forming the second distance.
摘要翻译：实施例的半导体器件包括基板和形成在基板上的多个翅片。多个翅片被布置成使得比第一距离窄的第一距离和第二距离被重复。另外，多个散热片包括半导体区域，其中在形成第一距离的侧面中彼此面对的侧面的下部的杂质浓度高于形成第一距离的侧面彼此相对的侧表面的下部的杂质浓度第二距离。

46. 发明授权

US07535064B2 Semiconductor device having a fin and method of manufacturing the same 有权
标题翻译：具有翅片的半导体器件及其制造方法
公开(公告)号：US07535064B2
公开(公告)日：2009-05-19
申请号：US11401928
申请日：2006-04-12
申请人： Takashi Izumida
发明人： Takashi Izumida
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7851
摘要： A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a semiconductor substrate. The source region and drain region are formed at both end portions of the Fin. The first extension region is formed between the source region and the drain region within the Fin in contact with the source region. The second extension region is formed between the source region and the drain region within the Fin in contact with the drain region. The channel region is located between the first extension region and the second extension region within the Fin, a height of the Fin of the channel region being greater than a height of the Fin of each of the first extension region and the second extension region.
摘要翻译：半导体器件包括Fin，源极区和漏极区，第一延伸区，第二延伸区和沟道区。鳍形成在半导体衬底的主表面上。源极区域和漏极区域形成在鳍片的两个端部处。第一延伸区形成在与源极区域接触的鳍内的源极区域和漏极区域之间。第二延伸区域形成在与漏极区域接触的鳍内的源极区域和漏极区域之间。沟道区域位于鳍内的第一延伸区域和第二延伸区域之间，沟道区域的鳍的高度大于第一延伸区域和第二延伸区域中的每一个的鳍的高度。

47. 发明申请

US20070063224A1 Metal insulator semiconductor field effect transistor having fin structure 有权
标题翻译：具有翅片结构的金属绝缘体半导体场效应晶体管
公开(公告)号：US20070063224A1
公开(公告)日：2007-03-22
申请号：US11495885
申请日：2006-07-31
申请人： Takeshi Watanabe , Kimitoshi Okano , Takashi Izumida
发明人： Takeshi Watanabe , Kimitoshi Okano , Takashi Izumida
IPC分类号： H01L27/10 , H01L29/73 , H01L29/768 , H01L27/148
CPC分类号： H01L21/823437 , H01L21/823412 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device includes a fin-shaped semiconductor layer, a gate electrode section formed in a widthwise direction of the semiconductor layer with a gate insulation film interposed therebetween, the gate electrode section including a plurality of electrode materials having different work functions and stacked one another, and a channel section formed adjacent to the gate insulation film in the semiconductor layer. The semiconductor device further includes source and drain regions formed adjacent to the channel section.
摘要翻译：半导体器件包括鳍状半导体层，在半导体层的宽度方向上形成有栅极绝缘膜的栅电极部，栅电极部分包括具有不同功函数且彼此堆叠的多个电极材料以及与半导体层中的栅极绝缘膜相邻形成的沟道部。半导体器件还包括与沟道部分相邻形成的源区和漏区。

48. 发明申请

US20060244051A1 Semiconductor manufacturing method and semiconductor device 有权
标题翻译：半导体制造方法和半导体器件
公开(公告)号：US20060244051A1
公开(公告)日：2006-11-02
申请号：US11203425
申请日：2005-08-15
申请人： Takashi Izumida , Sanae Ito , Takahisa Kanemura
发明人： Takashi Izumida , Sanae Ito , Takahisa Kanemura
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78609
摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
摘要翻译：制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

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