会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 43. 发明授权
    • High speed logic simulation system using time division emulation
suitable for large scale logic circuits
    • 高速逻辑仿真系统采用适合大规模逻辑电路的时分仿真
    • US5572710A
    • 1996-11-05
    • US120220
    • 1993-09-13
    • Shigehiro AsanoShouzou IsobeJiro AmemiyaHirofumi Muratani
    • Shigehiro AsanoShouzou IsobeJiro AmemiyaHirofumi Muratani
    • G06F17/50G06F17/00G06F9/455
    • G06F17/5027G06F17/5022Y10S706/92Y10S706/921
    • A logic simulation system capable of handling a very large scale circuit while realizing a high speed simulation by retaining the parallelism of the simulation targets. The system includes: a host computer having data of the simulation target divided into a plurality of sections defining different simulation phases to be executed sequentially in time division; an emulator for emulating the simulation target, including: a plurality of programmable emulation chips for mapping the simulation target, each emulation chip having a memory with a plurality of memory banks provided in correspondence to the plurality of sections for registering mapping data specifying a function to be realized by each emulation chip in emulating each of the plurality of sections; a programmable network for interconnecting the plurality of emulation chips; and an emulation control unit for controlling the plurality of emulation chips and the network by sequentially switching the memory banks of the memory of each emulation chip and changing connections among the plurality of emulation chips provided by the network in emulating each of the plurality of sections; and an interface unit for interfacing the host computer and the emulator.
    • 一种逻辑仿真系统,能够通过保持模拟目标的并行性实现高速仿真,处理大规模电路。 该系统包括:具有模拟目标的数据的主计算机,被划分为定义不同模拟阶段的多个部分,以便按时间顺序执行; 用于仿真所述模拟目标的仿真器,包括:用于映射所述模拟目标的多个可编程仿真芯片,每个仿真芯片具有存储器,所述存储器具有与所述多个部分对应地设置的多个存储体,用于将指定功能的映射数据注册到 每个仿真芯片在模拟多个部分中的每个部分时实现; 用于互连所述多个仿真芯片的可编程网络; 以及仿真控制单元,用于通过顺序地切换每个仿真芯片的存储器的存储器并且改变由所述网络提供的所述多个仿真芯片中的模拟所述多个部分中的每一个的连接,来控制所述多个仿真芯片和所述网络; 以及用于连接主计算机和仿真器的接口单元。
    • 46. 发明申请
    • Cryptographic protocol security verification apparatus, cryptographic protocol design apparatus, cryptographic protocol security verification method, cryptographic protocol design method and computer program product
    • 加密协议安全验证装置,加密协议设计装置,加密协议安全验证方法,加密协议设计方法和计算机程序产品
    • US20070098151A1
    • 2007-05-03
    • US11488942
    • 2006-07-18
    • Hirofumi Muratani
    • Hirofumi Muratani
    • H04L9/28H04L9/00H04K1/00
    • H04L9/3247H04L9/3273H04L63/0428H04L63/1433
    • A cryptographic protocol security verification apparatus includes a formal verification unit verifying a presence or absence of a defect of a process for a party and a first virtual entity based on a description of a verifiable cryptographic protocol specification data, wherein the verifiable cryptographic protocol specification data includes a first description section containing a description of a process for the party actually involved in the execution of a cryptographic protocol, and a second description section, where the second description section corresponds to an ideal protocol defined by an universal composability and containing the description of the process for the party actually involved in the execution of the cryptographic protocol and a first virtual entity not actually involved in the execution of the cryptographic protocol, and does not contain a description for a second virtual entity not actually involved in the execution of the cryptographic protocol, and wherein the first virtual entity corresponds to an ideal functionality of the ideal protocol, and the second virtual entity corresponds to a simulator of the ideal protocol.
    • 密码协议安全验证装置包括形式验证单元,其基于对可验证密码协议规范数据的描述来验证一方和第一虚拟实体的进程的缺陷的存在与否,其中,所述可验证密码协议规范数据包括 第一描述部分,其包含实际涉及执行密码协议的方的过程的描述,以及第二描述部分,其中第二描述部分对应于由通用可组合性定义的理想协议,并且包含 执行加密协议的方的实际过程和不实际涉及密码协议执行的第一虚拟实体,并且不包含实际上并不涉及密码协议执行的第二虚拟实体的描述 ,并且其中th e第一虚拟实体对应于理想协议的理想功能,并且第二虚拟实体对应于理想协议的模拟器。