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41. 发明授权

US06930545B2 Switched-capacitor, common-mode feedback circuit for a differential amplifier without tail current 失效
标题翻译：开关电容，共模反馈电路，用于不带尾电流的差分放大器
公开(公告)号：US06930545B2
公开(公告)日：2005-08-16
申请号：US10918550
申请日：2004-08-16
申请人： Tom W. Kwan , Ralph Duncan , Frank W. Singor
发明人： Tom W. Kwan , Ralph Duncan , Frank W. Singor
IPC分类号： H03F3/00 , H03F3/45 , H03F1/02
CPC分类号： H03F3/45645 , H03F3/005 , H03F3/45179 , H03F3/45188 , H03F3/45654 , H03F2203/45394 , H03F2203/45421 , H03F2203/45651
摘要： Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least one output port. The output port is configured to output an adjusting signal. The input signals includes a number of primary signals and two or more reference signals that are associated with a first timing phase of operation. The adjusting signal is produced based upon a comparison between the primary signals the reference signals. Also provided is a pair of active devices having gates coupled together and structured to receive the adjusting signal. The active devices are configured to provide a gain to the adjusting signal in accordance with a predetermined gain factor, and facilitate an adjustment to the number of primary signals based upon the gain during a second timing phase of operation.
摘要翻译：提供了一种开关电容器反馈电路，其包括被配置为接收对应的多个输入信号和至少一个输出端口的两个或多个输入端口。输出端口配置为输出调整信号。输入信号包括与第一定时相位相关联的多个主信号和两个或更多个参考信号。基于主信号之间的参考信号的比较产生调整信号。还提供了一对具有耦合在一起并被构造成接收调节信号的门的有源器件。有源器件被配置为根据预定的增益因子向调整信号提供增益，并且有助于在操作的第二定时阶段期间基于增益来调整主信号的数量。

42. 发明授权

US06828860B2 Gigabit ethernet transceiver with analog front end 有权
公开(公告)号：US06828860B2
公开(公告)日：2004-12-07
申请号：US10695099
申请日：2003-10-28
申请人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G310
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

43. 发明授权

US06781451B2 Switched-capacitor, common-mode feedback circuit for a differential amplifier without tail current 失效
标题翻译：开关电容，共模反馈电路，用于不带尾电流的差分放大器
公开(公告)号：US06781451B2
公开(公告)日：2004-08-24
申请号：US10425719
申请日：2003-04-30
申请人： Tom W. Kwan , Ralph Duncan , Frank W. Singor
发明人： Tom W. Kwan , Ralph Duncan , Frank W. Singor
IPC分类号： H03F102
CPC分类号： H03F3/45645 , H03F3/005 , H03F3/45179 , H03F3/45188 , H03F3/45654 , H03F2203/45394 , H03F2203/45421 , H03F2203/45651
摘要： Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least one output port. The output port is configured to output an adjusting signal. The input signals includes a number of primary signals and two or more reference signals that are associated with a first timing phase of operation. The adjusting signal is produced based upon a comparison between the primary signals the reference signals. Also provided is a pair of active devices having gates coupled together and structured to receive the adjusting signal. The active devices are configured to provide a gain to the adjusting signal in accordance with a predetermined gain factor, and facilitate an adjustment to the number of primary signals based upon the gain during a second timing phase of operation.
摘要翻译：提供了一种开关电容器反馈电路，其包括被配置为接收对应的多个输入信号和至少一个输出端口的两个或多个输入端口。输出端口配置为输出调整信号。输入信号包括与第一定时相位相关联的多个主信号和两个或更多个参考信号。基于主信号之间的参考信号的比较产生调整信号。还提供了一对具有耦合在一起并被构造成接收调节信号的门的有源器件。有源器件被配置为根据预定的增益因子向调整信号提供增益，并且有助于在操作的第二定时阶段期间基于增益来调整主信号的数量。

44. 发明授权

US06426680B1 System and method for narrow band PLL tuning 有权
标题翻译：具有改进的调谐范围超过过程和温度变化的集成VCO
公开(公告)号：US06426680B1
公开(公告)日：2002-07-30
申请号：US09580014
申请日：2000-05-26
申请人： Ralph Duncan , Tom W. Kwan
发明人： Ralph Duncan , Tom W. Kwan
IPC分类号： H03L7099
CPC分类号： H03L7/23 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/08 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H03B5/1209 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/364 , H03B2200/0038 , H03B2201/025 , H03B2201/0266 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L1/023 , H03L7/10 , H01L2924/00
摘要： An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.
摘要翻译：具有改进的调谐范围超过过程和温度变化的集成VCO。因此，在本发明的本实施例中提供了集成VCO。 VCO包括：衬底，响应于设置在衬底上的VCO状态变量的VCO调谐控制电路，以及设置在衬底上的VCO，具有落在VCO调谐范围内的调谐控制电压输入，用于调节VCO频率输出，并且其调谐范围由调谐控制电路响应于VCO状态变量而调整。

45. 发明授权

US6141671A Asynchronous digital sample rate converter 失效
标题翻译：异步数字采样率转换器
公开(公告)号：US6141671A
公开(公告)日：2000-10-31
申请号：US653125
申请日：1996-05-24
申请人： Robert W. Adams , Tom W. Kwan , Michael Coln
发明人： Robert W. Adams , Tom W. Kwan , Michael Coln
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06 , G06F17/17
CPC分类号： H03H17/0628
摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.
摘要翻译：异步数字采样率转换器包括用于存储输入数据值的随机存取存储器和用于存储缩减的一组内插滤波器系数的只读存储器。输入数据以输入采样率写入随机存取存储器。输出样本由给定输入数据流的乘法/累加引擎提供，滤波器系数根据请求在输出频率下产生输出采样。用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的一阶闭环系统输出采样率。这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。该电路包括一种消除噪声的数字滞后形式。通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。

46. 发明授权

US08841963B2 Gigabit ethernet transceiver with analog front end 有权
标题翻译：具有模拟前端的千兆以太网收发器
公开(公告)号：US08841963B2
公开(公告)日：2014-09-23
申请号：US11345946
申请日：2006-02-02
申请人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03K5/00 , H03H11/24 , H03F1/32 , H03G3/30 , H03F3/50 , H03G3/00 , H03F3/347 , H03G1/00 , H03G5/10
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
摘要翻译：电路从集成电路可编程增益衰减器中的信号路径中去除开关。可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。这种开关可能在信号中引入非线性。通过将开关与信号路径隔离，可以提高PGA的线性度。

47. 发明申请

US20140176482A1 CAPACITIVE TOUCH SENSING SYSTEM WITH INTERFERENCE REJECTION 有权
标题翻译：具有干扰抑制的电容触摸感应系统
公开(公告)号：US20140176482A1
公开(公告)日：2014-06-26
申请号：US13754632
申请日：2013-01-30
申请人： Guo Wen Wei , Tom W. Kwan
发明人： Guo Wen Wei , Tom W. Kwan
IPC分类号： G06F3/044
CPC分类号： G06F3/044 , G06F3/0418
摘要： An interference tolerant capacitive touch sensor readout circuit having improved power and area efficiency is disclosed. Interference rejection for the capacitive touch sensing system is realized by transferring charge between a capacitive touch sensor and the readout circuit at frequencies outside bands where a level of interference is unacceptable. Improved power and area efficient come from the simplicity of the readout circuit which comprises a switched-capacitor integrator, a comparator, a digital accumulator and number of switches for driving a touch sensor and a capacitive feedback loop. The readout circuit is capable of interfacing with both self and mutual capacitance sensor to achieve compatibility with a larger collection of sensors and provides additional sensing and diagnostic functionalities.
摘要翻译：公开了具有改进的功率和面积效率的抗干扰电容式触摸传感器读出电路。通过在电容式触摸传感器和读出电路之间的频率外的频率处传输电荷来实现电容式触摸感测系统的干扰抑制，其中干扰水平是不可接受的。改进的功率和面积效率来自包括开关电容积分器，比较器，数字累加器和用于驱动触摸传感器和电容反馈回路的开关数量的读出电路的简单性。读出电路能够与自相互电容传感器和互电容传感器接口，以实现与较大传感器的兼容性，并提供额外的感测和诊断功能。

48. 发明授权

US08614621B2 Remote control for multimedia system having touch sensitive panel for user ID 有权
标题翻译：具有用于用户ID的触敏面板的多媒体系统的遥控器
公开(公告)号：US08614621B2
公开(公告)日：2013-12-24
申请号：US12912405
申请日：2010-10-26
申请人： David A. Sobel , Qiang Fu , Sumant Ranganathan , John Walley , Pieter Vorenkamp , Jeyhan Karaoguz , Tom W. Kwan
发明人： David A. Sobel , Qiang Fu , Sumant Ranganathan , John Walley , Pieter Vorenkamp , Jeyhan Karaoguz , Tom W. Kwan
IPC分类号： G06F3/041 , G06F13/00 , G06F7/04
CPC分类号： G06F3/033 , G06F21/32
摘要： Operating a remote control to identify a user by receiving touch pad input from at least one touch sensitive element of the remote control that has a plurality of touch sensitive elements. The touch pad input corresponds to the user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the remote control and transmitted to a multimedia system console via a communications interface of the remote control for processing of the at least partially processed touch pad input to identify the user via pattern recognition. At least partially processing the touch pad input can be by identifying at least one finger orientation, at least one finger spacing, at least one finger width, a plurality of finger knuckle/joint locations, and/or a plurality of finger lengths based upon the touch pad input.
摘要翻译：通过从具有多个触敏元件的遥控器的至少一个触敏元件接收触摸板输入来操作遥控器以识别用户。触摸板输入对应于用户对多个触敏元件中的至少一些的触摸。所述触摸板输入至少部分地由所述遥控器的处理电路处理，并且经由所述遥控器的通信接口传送到多媒体系统控制台，用于处理所述至少部分经过处理的触摸板输入以经由模式识别识别所述用户。至少部分地处理触摸板输入可以通过基于所述至少一个手指定向，至少一个手指间隔，至少一个手指宽度，多个指关节/关节位置和/或多个手指长度来识别触摸板输入。

49. 发明授权

US08000083B2 Scalable integrated circuit high density capacitors 失效
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US08000083B2
公开(公告)日：2011-08-16
申请号：US12511398
申请日：2009-07-29
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01G4/06
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或用于形成电容器的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

50. 发明授权

US07710300B2 Segmented data shuffler apparatus for a digital to analog converter (DAC) 有权
标题翻译：用于数模转换器（DAC）的分段数据洗牌装置
公开(公告)号：US07710300B2
公开(公告)日：2010-05-04
申请号：US12081547
申请日：2008-04-17
申请人： Tom W. Kwan
发明人： Tom W. Kwan
IPC分类号： H03M3/00 , H03M1/66
CPC分类号： H03M3/416 , H03M3/50 , H03M7/3026
摘要： A sigma-delta digital to analog converter (DAC) module converts the digital input signal to the analog output signal through segmentation, including a primary and a secondary sigma-delta modulator. The primary sigma-delta modulator produces a primary digital segment and a primary quantization error. A primary sample is delayed, decoded, scrambled and converted to produce a primary analog segment. A secondary sigma-delta modulates the primary quantization error to produce a secondary digital segment which is noise shaped by a noise transfer function of the primary sigma-delta modulator to produce a noise shaped secondary digital segment which is decoded, scrambled, converted and scaled to produce a secondary analog segment. An adder combines the primary analog segment and the secondary analog segment to produce the analog output signal.
摘要翻译： Σ-Δ数模转换器（DAC）模块通过包括初级和次级Σ-Δ调制器的分段将数字输入信号转换成模拟输出信号。初级Σ-Δ调制器产生主数字段和主量化误差。主要样本被延迟，解码，加扰和转换以产生主要的模拟段。次级Σ-Δ调制主量化误差以产生次级数字段，其由主要Σ-Δ调制器的噪声传递函数进行噪声整形，以产生噪声形状的次级数字段，其被解码，加扰，转换和缩放为产生二次模拟段。一个加法器结合了主要的模拟段和二级模拟段，以产生模拟输出信号。

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