会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 41. 发明授权
    • Electrode materials with improved hydrogen degradation resistance
    • 具有改善耐氢降解性的电极材料
    • US06833572B2
    • 2004-12-21
    • US10229603
    • 2002-08-27
    • Fengyan ZhangTingkai LiHong YingYoshi OnoSheng Teng Hsu
    • Fengyan ZhangTingkai LiHong YingYoshi OnoSheng Teng Hsu
    • H01L2976
    • H01L28/75H01L21/31604H01L21/31683H01L28/55
    • An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.
    • 用于铁电体器件的电极包括底部电极; 铁电层 以及形成在强电介质层上并由金属组合形成的顶部电极,其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层,并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。 在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。
    • 43. 发明授权
    • MSM binary switch memory
    • MSM二进制开关存储器
    • US07608514B2
    • 2009-10-27
    • US11900999
    • 2007-09-15
    • Sheng Teng HsuTingkai Li
    • Sheng Teng HsuTingkai Li
    • H01L21/336
    • H01L27/101G11C13/0007G11C2213/31H01L27/2409H01L27/2463H01L29/66143H01L29/872H01L45/04H01L45/1233H01L45/147
    • A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.
    • 提供金属/半导体/金属(MSM)二进制开关存储器件和制造工艺。 该器件包括存储器电阻器底部电极,存储器电阻器底部电极上方的存储器电阻器材料,以及存储器电阻器材料上的存储器电阻器顶部电极。 MSM底部电极覆盖存储电阻器顶部电极,半导体层覆盖在MSM底部电极上,并且MSM顶部电极覆盖半导体层。 MSM底部电极可以是诸如Pt,Ir,Au,Ag,TiN或Ti的材料。 MSM顶部电极可以是诸如Pt,Ir,Au,TiN,Ti或Al的材料。 半导体层可以是非晶Si,ZnO 2或InO 2。
    • 44. 发明授权
    • Rare earth element-doped oxide precursor with silicon nanocrystals
    • 具有硅纳米晶体的稀土元素掺杂氧化物前体
    • US07585788B2
    • 2009-09-08
    • US11224549
    • 2005-09-12
    • Wei-Wei ZhuangYoshi OnoSheng Teng HsuTingkai Li
    • Wei-Wei ZhuangYoshi OnoSheng Teng HsuTingkai Li
    • H01L21/31
    • H01L21/02156H01L21/02282H01L21/316
    • A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si particles; mixing a second organic solvent having a second boiling point, higher than the first boiling point, to the filtered first solution; and, fractionally distilling, forming a second solution of nc Si particles. The Si particles are formed by immersing a Si wafer into a third solution including hydrofluoric (HF) acid and alcohol, applying an electric bias, and forming a porous Si layer overlying the Si wafer. Then, the Si particles are mixed into the organic solvent by depositing the Si wafer into the first organic solvent, and ultrasonically removing the porous Si layer from the Si wafer.
    • 提供了一种用于形成具有纳米晶体(nc)Si颗粒的稀土元素掺杂的氧化硅(SiO 2)前体的方法。 一方面,该方法包括:将Si颗粒混合到第一有机溶剂中,形成具有第一沸点的第一溶液; 过滤第一溶液以除去大的Si颗粒; 将具有高于第一沸​​点的第二沸点的第二有机溶剂与过滤的第一溶液混合; 并分馏,形成nc Si颗粒的第二溶液。 通过将Si晶片浸入包括氢氟酸(HF)酸和醇的第三溶液中,施加电偏压并形成覆盖Si晶片的多孔Si层,形成Si颗粒。 然后,通过将Si晶片沉积到第一有机溶剂中,将Si颗粒混入有机溶剂中,并从Si晶片超声波除去多孔Si层。
    • 45. 发明申请
    • Gallium nitride-on-silicon interface
    • 氮化镓在硅界面
    • US20080280426A1
    • 2008-11-13
    • US11801210
    • 2007-05-09
    • Tingkai LiDouglas J. TweetJer-Shen MaaSheng Teng Hsu
    • Tingkai LiDouglas J. TweetJer-Shen MaaSheng Teng Hsu
    • H01L29/739H01L21/20
    • C30B29/406C30B25/183H01L21/02381H01L21/02458H01L21/02505H01L21/0254H01L21/02642H01L21/02647H01L29/2003H01L29/267
    • A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.
    • 提供了一种在硅(Si)和氮化镓(GaN)膜之间形成匹配的热膨胀界面的方法。 该方法提供(111)Si衬底并且在压缩覆盖Si衬底上形成第一含铝(Al)的膜。 在第一含Al膜中形成纳米柱孔,其暴露下面的Si衬底的区域。 从暴露区域选择性地生长GaN层,覆盖第一含Al膜。 使用横向纳米外延生长(LNEO)工艺生长GaN。 重复上述过程,在压缩中形成第二含Al膜,在第二含Al膜中形成纳米柱孔,并选择性地生长第二GaN层。 可以最初在低温下生长诸如Al 2 O 3 3,Si 1-x Ge x,InP,GaP,GaAs,AlN,AlGaN或GaN的膜材料。 通过增加生长温度,可以在Si衬底上形成外延GaN的压缩层。
    • 47. 发明授权
    • Electroluminescence device with nanotip diodes
    • 具有纳米二极管的电致发光器件
    • US07320897B2
    • 2008-01-22
    • US11090386
    • 2005-03-23
    • Sheng Teng HsuTingkai LiWei-Wei Zhuang
    • Sheng Teng HsuTingkai LiWei-Wei Zhuang
    • H01L21/66
    • H01L33/08B82Y20/00H01L33/18H01L33/24H01L33/34H01L33/502Y10S977/834
    • A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.
    • 提供了一种纳米末端电致发光(EL)二极管和一种用于制造所述器件的方法。 该方法包括:形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。 纳米二极管通过以下方式形成:形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米(nm)的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻(RIE)诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模,蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。
    • 49. 发明授权
    • Ferroelectric resistor non-volatile memory array
    • 铁电电阻非易失性存储器阵列
    • US06819583B2
    • 2004-11-16
    • US10345726
    • 2003-01-15
    • Sheng Teng HsuTingkai LiFengyan Zhang
    • Sheng Teng HsuTingkai LiFengyan Zhang
    • G11C1122
    • G11C11/22
    • A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.
    • 铁基薄膜电阻存储阵列形成在基板上,并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括:具有一对端子的FE电阻器和与每个电阻器相关联的晶体管,其中每个晶体管具有栅极,漏极和源极,并且其中每个晶体管的漏极电连接到 其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。
    • 50. 发明授权
    • Deposition method for lead germanate ferroelectric structure with multi-layered electrode
    • 具有多层电极的锗酸铅铁电结构沉积方法
    • US06759250B2
    • 2004-07-06
    • US10196503
    • 2002-07-15
    • Fengyan ZhangTingkai LiSheng Teng Hsu
    • Fengyan ZhangTingkai LiSheng Teng Hsu
    • H01L2100
    • H01L28/56H01L21/31604H01L21/31691H01L28/75
    • The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.
    • 提供了包括与锗酸铅(Pb5Ge3O11)薄膜结合使用的Pt / Ir层叠电极的铁电体结构。 该电极对基材表现出良好的粘合性,并且对氧和铅具有阻挡性能。 在MOCVD锗酸铅(Pb5Ge3O11)薄膜工艺中,通过使用在原位形成的薄的IrO 2层,铁电性能得到改善,而不损害漏电流。 通过使用Pt / Ir电极,需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅(Pb5Ge3O11)薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅(Pb5Ge3O11)薄膜的温度范围为400-500℃。与使用单层铱电极相比,获得了较大的成核密度。 因此,锗酸铅(Pb5Ge3O11)薄膜表面光滑,微观组织均匀,铁电性能均匀。 还提供了形成上述多层电极铁电体结构体的方法。