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41. 发明申请

US20100283121A1 ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS 有权
标题翻译：具有分层尺寸的电熔丝和电阻
公开(公告)号：US20100283121A1
公开(公告)日：2010-11-11
申请号：US12765275
申请日：2010-04-22
申请人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
发明人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L27/101 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要翻译：提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。包括导体或半导体的导电结构形成在半导体衬底上。在导电结构上形成至少一个绝缘体层。在所述至少一个绝缘体层中形成凹陷区域。将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

42. 发明授权

US07829452B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07829452B2
公开(公告)日：2010-11-09
申请号：US12348934
申请日：2009-01-06
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

43. 发明申请

US20100032829A1 STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于改善半导体器件中的焊接保护连接的结构和方法
公开(公告)号：US20100032829A1
公开(公告)日：2010-02-11
申请号：US12187646
申请日：2008-08-07
申请人： Felix P. Anderson , William Cote , Daniel C. Edelstein , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , William Cote , Daniel C. Edelstein , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/13 , H01L21/3105 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L23/53238 , H01L23/53295 , H01L24/11 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2221/1036 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05647 , H01L2224/05666 , H01L2224/13022 , H01L2224/13027 , H01L2224/13099 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/45147 , H01L2224/48847 , H01L2924/00011 , H01L2924/01005 , H01L2924/01014 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/19042 , H01L2924/00014 , H01L2924/00 , H01L2924/01006
摘要： Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.
摘要翻译：具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。该结构包括在至少一部分没有氟边界层的电介质层中形成的沟槽。该结构还包括在沟槽中的铜线，其至少其底部与沟槽的非氟化物边界层接触。无铅焊料凸块与铜线电接触。

44. 发明申请

US20090155993A1 TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME 有权
标题翻译：端子板结构及其制造方法
公开(公告)号：US20090155993A1
公开(公告)日：2009-06-18
申请号：US12348934
申请日：2009-01-06
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/60
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

45. 发明申请

US20080254630A1 DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于减少半导体器件中有效介电常数的器件和方法
公开(公告)号：US20080254630A1
公开(公告)日：2008-10-16
申请号：US12139803
申请日：2008-06-16
申请人： Daniel C. EDELSTEIN , Matthew E. Colburn , Edward C. Cooney , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. EDELSTEIN , Matthew E. Colburn , Edward C. Cooney , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/311
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
摘要翻译：制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成亚光刻特征跨越至少一个互连的侧壁。

46. 发明授权

US07394110B2 Planar vertical resistor and bond pad resistor 有权
标题翻译：平面垂直电阻和接合焊盘电阻
公开(公告)号：US07394110B2
公开(公告)日：2008-07-01
申请号：US11307404
申请日：2006-02-06
申请人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
发明人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L23/62
CPC分类号： H01L28/20 , H01L23/5228 , H01L23/53238 , H01L23/53295 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要翻译：公开了避免半导体器件小型化的问题的电阻器及相关方法。在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。这两个实施方案可以单独使用或一起使用。还公开了用于产生电阻器的相关方法。

47. 发明授权

US07361993B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07361993B2
公开(公告)日：2008-04-22
申请号：US10908346
申请日：2005-05-09
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/40
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

48. 发明授权

US07351639B2 Increasing an electrical resistance of a resistor by oxidation or nitridization 有权
公开(公告)号：US07351639B2
公开(公告)日：2008-04-01
申请号：US10753241
申请日：2004-01-08
申请人： Arne W. Ballantine , Daniel C. Edelstein , Anthony K. Stamper
发明人： Arne W. Ballantine , Daniel C. Edelstein , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： C23C8/02 , C23C8/04 , C23C8/10 , C23C8/24 , C25D11/00 , C25D11/02 , C25D11/026 , H01C7/006 , H01C17/26 , H01L21/263 , H01L27/0802 , H01L29/8605 , Y10S257/904 , Y10S257/914
摘要： A method and structure for increasing an electrical resistance of a resistor that is within a semiconductor structure, by oxidizing or nitridizing a fraction of a surface layer of the resistor with oxygen/nitrogen (i.e., oxygen or nitrogen) particles, respectively. The semiconductor structure may include a semiconductor wafer, a semiconductor chip, and an integrated circuit. The method and structure comprises five embodiments. The first embodiment comprises heating an interior of a heating chamber that includes the oxygen/nitrogen particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen). The second embodiment comprises heating the fraction of the surface layer by a beam of radiation (e.g., laser radiation), or a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen/particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen). The third embodiment comprises: using a plasma chamber to generate plasma oxygen/nitrogen ions; and applying a DC voltage to the plasma oxygen/nitrogen ions to accelerate the plasma oxygen/nitrogen ions into the resistor such that the oxygen/nitrogen particles include the plasma oxygen/nitrogen ions. The fourth embodiment comprises using an anodization circuit to electrolytically generate oxygen/nitrogen ions in an electrolytic solution in which the resistor is immersed, wherein the oxygen/nitrogen particles include the electrolytically-generated oxygen/nitrogen ions. The fifth embodiment comprises immersing the semiconductor structure in a chemical solution which includes the oxygen/nitrogen particles, wherein the oxygen/nitrogen particles may include oxygen/nitrogen-comprising liquid molecules, oxygen/nitrogen ions, or an oxygen/nitrogen-comprising gas dissolved in the chemical solution under pressurization.

49. 发明授权

US07327033B2 Copper alloy via bottom liner 有权
标题翻译：铜合金通过底衬
公开(公告)号：US07327033B2
公开(公告)日：2008-02-05
申请号：US10710828
申请日：2004-08-05
申请人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
发明人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
IPC分类号： H01L23/52
CPC分类号： H01L23/53238 , H01L23/5226 , H01L2924/0002 , Y10T428/12493 , H01L2924/00
摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.
摘要翻译：通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

50. 发明授权

US07081680B2 Self-aligned corrosion stop for copper C4 and wirebond 有权
标题翻译：用于铜C4和引线键的自对准腐蚀停止
公开(公告)号：US07081680B2
公开(公告)日：2006-07-25
申请号：US10849459
申请日：2004-05-19
申请人： Daniel C. Edelstein , Anthony K. Stamper , Judith M. Rubino , Carlos J. Sambucetti
发明人： Daniel C. Edelstein , Anthony K. Stamper , Judith M. Rubino , Carlos J. Sambucetti
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/48 , H01L21/288 , H01L21/32134 , H01L21/4846 , H01L21/76886 , H01L23/498 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/45 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05016 , H01L2224/05073 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05184 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48755 , H01L2224/48764 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H05K3/244 , Y10T29/49117 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2224/05552
摘要： An electrical structure including a substrate and an interconnect. The substrate includes an electrically conductive and corrosion resistant metallic layer on a metal layer. The interconnect is electrically coupled to the metallic layer. A top surface of the metallic layer is above a top surface of the substrate and a bottom surface of the metallic layer is in direct mechanical contact with a first portion of a top surface of the metal layer. The metal layer is unalloyed and includes a metal.
摘要翻译：包括衬底和互连的电结构。衬底包括在金属层上的导电且耐腐蚀的金属层。互连电耦合到金属层。金属层的顶表面位于衬底的顶表面之上，并且金属层的底表面与金属层的顶表面的第一部分直接机械接触。金属层是非合金的并且包括金属。

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