会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 42. 发明授权
    • Multiple-word multiplication-accumulation circuit and montgomery modular multiplication-accumulation circuit
    • 多字乘法积累电路和montgomery模乘法积累电路
    • US08078661B2
    • 2011-12-13
    • US10898178
    • 2004-07-26
    • Kenji MukaidaMasahiko TakenakaNaoya ToriiShoichi Masui
    • Kenji MukaidaMasahiko TakenakaNaoya ToriiShoichi Masui
    • G06F7/38
    • G06F7/728G06F7/5443
    • A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. The registers serve as buffer storage of multiple-word data to be supplied to individual input ports of the MAC operator. The amount of data supplied to the MAC operator in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle will be equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. This feature enables the use of a bandwidth-limited single-port memory, without causing adverse effect on the efficiency of MAC operator usage.
    • 适用于单端口存储器的多字乘法积累电路。 该电路由乘积(MAC)运算符和周围寄存器组成。 MAC运算符具有不同位宽的乘法器和乘法器输入端口,以计算从存储器读出的多个字数据的乘积之和。 这些寄存器用作缓冲存储多字数据以提供给MAC操作员的各个输入端口。 调整在每个时钟周期内提供给MAC运算符的数据量,使得MAC运算符在一个时钟周期内消耗和产生的数据总量将等于或小于存储器可以传输的最大数据量 一个时钟周期。 该功能使得能够使用带宽限制的单端口存储器,而不会对MAC操作者使用的效率造成不利影响。
    • 43. 发明授权
    • Encryption/decryption system for calculating effective lower bits of a parameter for Montgomery modular multiplication
    • 加密/解密系统,用于计算Montgomery模数乘法的参数的有效低位
    • US07403965B2
    • 2008-07-22
    • US10888991
    • 2004-07-13
    • Kenji MukaidaMasahiko TakenakaNaoya ToriiShoichi Masui
    • Kenji MukaidaMasahiko TakenakaNaoya ToriiShoichi Masui
    • G06F7/00
    • G06F7/728
    • An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND, the parameter ND satisfying R×R−1−N×ND=1 for an integer N and a radix R that is coprime to and greater than N, with a large number of effective lower bits. The device comprises an ND generator, a multiplication-accumulation (MAC) operator, and a sum data store. The ND generator produces effective lower bits of ND at a rate of k bits per clock cycle, with reference to lower k bits of a variable S, as well as to lower k bits of an odd positive integer N. The MAC operator multiplies the produced k-bit ND value by N and adds the resulting product to S. The sum data store stores the variable S, which is updated with the output of the MAC operator, with its bits shifted right by k bits, for use by the ND generator in the subsequent clock cycle.
    • 一种用于蒙哥马利模乘的运算装置,其快速计算参数ND,对于整数N满足RxR -1 -NxND = 1的参数ND和与N并且大于N的基数R, 大量有效的低位。 该装置包括ND发生器,乘积累加(MAC)运算符和和数据存储。 ND发生器以每个时钟周期的k比特的速率产生有效的低位,参考变量S的低k位,以及降低奇数正整数N的k位。MAC算子将所产生的 k位ND值乘以N,并将所得到的乘积加到S中。和数据存储器存储用MAC运算符的输出更新的变量S,其位被向右移位k位,供ND生成器使用 在随后的时钟周期。
    • 45. 发明申请
    • Arithmetic device
    • 算术设备
    • US20050165875A1
    • 2005-07-28
    • US10888991
    • 2004-07-13
    • Kenji MukaidaMasahiko TakenakaNaoya ToriiShoichi Masui
    • Kenji MukaidaMasahiko TakenakaNaoya ToriiShoichi Masui
    • G06F7/72G09C1/00G06F7/00
    • G06F7/728
    • An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND with a large number of effective lower bits. The device comprises an ND generator, a multiplication-accumulation (MAC) operator, and a sum data store. The ND generator produces effective lower bits of ND at a rate of k bits per clock cycle, with reference to lower k bits of a variable S, as well as to lower k bits of an odd positive integer N. The MAC operator multiplies the produced k-bit ND value by N and adds the resulting product to S. The sum data store stores the variable S, which is updated with the output of the MAC operator, with its bits shifted right by k bits, for use by the ND generator in the subsequent clock cycle.
    • 一种用于蒙哥马利模数乘法的运算装置,它可以快速计算具有大量有效低位的参数ND。 该装置包括ND发生器,乘积累加(MAC)运算符和和数据存储。 ND发生器以每个时钟周期的k比特的速率产生有效的低位,参考变量S的低k位,以及降低奇数正整数N的k位。MAC算子将所产生的 k位ND值乘以N,并将所得到的乘积加到S中。和数据存储器存储用MAC运算符的输出更新的变量S,其位被向右移位k位,供ND生成器使用 在随后的时钟周期。
    • 48. 发明授权
    • Encryption secured against DPA
    • 针对DPA的加密
    • US07386130B2
    • 2008-06-10
    • US10028265
    • 2001-12-28
    • Koichi ItoMasahiko TakenakaNaoya Torii
    • Koichi ItoMasahiko TakenakaNaoya Torii
    • H04L9/00H04K1/00
    • H04L9/003H04L2209/04H04L2209/12
    • The encryption device includes a random number generator for generating a random number; and a first selector for selecting one of q fixed values in response to the random number, a second selector for selecting one set of q sets of fixed S-box tables in response to the random number. An XOR XORs an input with an XOR of a key with the fixed value. A nonlinear transform transforms an input nonlinearly in accordance with the selected set of fixed S-box tables. Another encryption device includes a plurality of encrypting units coupled in parallel, and a selector for selecting one of the plurality of encrypting units in response to the random number. The masking with the fixed values improves the processing speed and reduces the required RAM area.
    • 加密装置包括用于产生随机数的随机数发生器; 以及第一选择器,用于响应于所述随机数来选择q个固定值之一;第二选择器,用于响应于所述随机数来选择一组q个固定S盒表。 异或运算具有固定值的键的XOR的输入。 非线性变换根据所选择的固定S盒表组非线性地变换输入。 另一个加密装置包括并行耦合的多个加密单元和用于响应于该随机数来选择多个加密单元之一的选择器。 具有固定值的屏蔽可提高处理速度,并减少所需的RAM区域。