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41. 发明申请

US20110202812A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110202812A1
公开(公告)日：2011-08-18
申请号：US12888822
申请日：2010-09-23
申请人： Shigehiro ASANO , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
发明人： Shigehiro ASANO , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
IPC分类号： G06F11/14
CPC分类号： G11C29/52 , G06F11/1008 , G06F11/1068
摘要： According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
摘要翻译：根据一个实施例，半导体存储器件包括要求写入数据的半导体存储器芯片。数据具有预定单元中的一个或多个第一数据。该装置包括写入控制器，其写入通过使用预定数量的第一数据计算出的第一数据和冗余信息，并将其用于将预定数量的第一数据中的错误校正到不同的半导体存储器芯片中; 以及存储单元，其存储相互关联的识别信息和区域指定信息。所述识别信息将所述第一数据和所述冗余信息相关联，并且所述区域指定信息指定所述第一数据和所述冗余信息相互写入的所述半导体存储器芯片中的多个存储区域。

42. 发明申请

US20110202578A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110202578A1
公开(公告)日：2011-08-18
申请号：US12885941
申请日：2010-09-20
申请人： Shigehiro ASANO , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
发明人： Shigehiro ASANO , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
IPC分类号： G06F17/30
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.
摘要翻译：根据一个实施例，半导体存储器件响应于从主机以指定的逻辑块地址写入数据的请求，执行将数据写入到半导体存储器元件，并且执行将有效数据写入半导体存储元件以进行压缩以日志结构的方式。半导体存储器装置根据预定的比例调整来自主机的请求的写入响应的频率和用于压缩的写入频率。

43. 发明授权

US08612721B2 Semiconductor memory controlling device 有权
标题翻译：半导体存储器控制装置
公开(公告)号：US08612721B2
公开(公告)日：2013-12-17
申请号：US13037970
申请日：2011-03-01
申请人： Shigehiro Asano , Shinichi Kanno , Kenichiro Yoshii
发明人： Shigehiro Asano , Shinichi Kanno , Kenichiro Yoshii
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/7201 , G06F2212/7205
摘要： According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.
摘要翻译：根据一个实施例，根据信息处理器的要求，半导体存储控制器以预定单位将多条数据写入在半导体芯片的存储区域内的擦除区域中没有数据写入的存储位置。作为其子集的第三表和第二表包括各自表示半导体芯片内的每个数据的存储位置的物理地址。第一表包括指定第二表条目的信息或指定第三表条目的信息。半导体存储控制器将第一和第二表记录到易失性存储器中，或将第一表记录到易失性存储器中，将第三表记录到非易失性存储器中。

44. 发明授权

US08495336B2 Controller, data storage device, and program product 有权
标题翻译：控制器，数据存储设备和程序产品
公开(公告)号：US08495336B2
公开(公告)日：2013-07-23
申请号：US12883796
申请日：2010-09-16
申请人： Kazuhiro Fukutomi , Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro Fukutomi , Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F13/12
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0611 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F3/0688 , G06F12/00 , G06F12/16 , G06F2212/1016 , G06F2212/214 , G06F2212/7202 , G06F2212/7205
摘要： According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
摘要翻译：根据一个实施例，写指令单元指示数据存取单元在由第一物理地址指示的数据存储单元的存储区中写入对象数据，指示管理信息访问单元更新地址转换信息，以及指示第一个访问单元更新第一个物理地址。压缩单元提取压缩对象数据的物理地址，指示数据访问单元读取由物理地址指示的数据存储单元的存储区域中存储的压缩对象数据，指示数据存取单元写入压缩对象数据在由第二物理地址指示的数据存储单元的存储区域中，指示管理信息存取单元更新地址转换信息，并指示第二存取单元更新第二物理地址。

45. 发明授权

US08448034B2 Semiconductor memory device 有权
公开(公告)号：US08448034B2
公开(公告)日：2013-05-21
申请号：US12888822
申请日：2010-09-23
申请人： Shigehiro Asano , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
发明人： Shigehiro Asano , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
IPC分类号： H04L1/00 , G06F11/00
CPC分类号： G11C29/52 , G06F11/1008 , G06F11/1068
摘要： According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.

46. 发明申请

US20120072644A1 SEMICONDUCTOR MEMORY CONTROLLING DEVICE 有权
标题翻译：半导体存储器控制器件
公开(公告)号：US20120072644A1
公开(公告)日：2012-03-22
申请号：US13037970
申请日：2011-03-01
申请人： Shigehiro ASANO , Shinichi Kanno , Kenichiro Yoshii
发明人： Shigehiro ASANO , Shinichi Kanno , Kenichiro Yoshii
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/7201 , G06F2212/7205
摘要： According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.
摘要翻译：根据一个实施例，根据信息处理器的要求，半导体存储控制器以预定单位将多条数据写入在半导体芯片的存储区域内的擦除区域中没有数据写入的存储位置。作为其子集的第三表和第二表包括各自表示半导体芯片内的每个数据的存储位置的物理地址。第一表包括指定第二表条目的信息或指定第三表条目的信息。半导体存储控制器将第一和第二表记录到易失性存储器中，或将第一表记录到易失性存储器中，将第三表记录到非易失性存储器中。

47. 发明申请

US20110231624A1 CONTROLLER, DATA STORAGE DEVICE, AND PROGRAM PRODUCT 有权
标题翻译：控制器，数据存储设备和程序产品
公开(公告)号：US20110231624A1
公开(公告)日：2011-09-22
申请号：US12883796
申请日：2010-09-16
申请人： Kazuhiro FUKUTOMI , Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro FUKUTOMI , Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F12/00 , G06F12/16 , G06F12/10
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0611 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F3/0688 , G06F12/00 , G06F12/16 , G06F2212/1016 , G06F2212/214 , G06F2212/7202 , G06F2212/7205
摘要： According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
摘要翻译：根据一个实施例，写指令单元指示数据存取单元在由第一物理地址指示的数据存储单元的存储区中写入对象数据，指示管理信息访问单元更新地址转换信息，以及指示第一个访问单元更新第一个物理地址。压缩单元提取压缩对象数据的物理地址，指示数据存取单元读取存储在由物理地址指示的数据存储单元的存储区域中的压缩对象数据，指示数据存取单元写入压缩对象数据在由第二物理地址指示的数据存储单元的存储区域中，指示管理信息存取单元更新地址转换信息，并指示第二存取单元更新第二物理地址。

48. 发明授权

US08516182B2 Controller and memory system for managing data 失效
标题翻译：用于管理数据的控制器和存储器系统
公开(公告)号：US08516182B2
公开(公告)日：2013-08-20
申请号：US12554272
申请日：2009-09-04
申请人： Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
发明人： Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7207 , G06F2212/7209
摘要： A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table.
摘要翻译：控制器包括用于转换表的存储器，其中显示闪存中的逻辑和物理地址彼此对应; 指示存储在每个块中的每个页面中存储的数据的状态的FAT信息和每个识别由FAT信息指示的状态中存储有数据的页面所属的块的FAT信息标识符，同时保持它们相互对应; 另一个用于表示块标识符的块管理表的存储器，指示是否使用相应块的使用状态判断信息以及与使用状态判断信息所使用的所有块对应的FAT信息标识符，而保持彼此对应; 以及控制器控制单元，通过使用转换表，FAT信息和块管理表来管理存储在闪速存储器中的数据。

49. 发明授权

US07069297B2 Data transfer scheme using re-direct response message for reducing network load 失效
公开(公告)号：US07069297B2
公开(公告)日：2006-06-27
申请号：US10396396
申请日：2003-03-26
申请人： Yasuhiro Kimura , Yuichi Koba , Kenichiro Yoshii , Atsushi Shono , Hideaki Sato , Toshibumi Seki
发明人： Yasuhiro Kimura , Yuichi Koba , Kenichiro Yoshii , Atsushi Shono , Hideaki Sato , Toshibumi Seki
IPC分类号： G06F13/00
CPC分类号： H04L67/16 , H04L29/06 , H04L67/14 , H04L67/2804 , H04L67/2814 , H04L67/2828 , H04L67/2842 , H04L69/22 , H04L69/329
摘要： At a data transfer device for transferring a request message from a first communication device to a second communication device, and transferring a response message containing a response data from the second communication device to the first communication device, an identifier to be allocated to the response data contained in the response message is generated according to a content of the response data, and a re-direct response message for re-directing the first communication unit to a URL containing the identifier is transmitted to the first communication device, instead of transmitting the response message, when the response message is received from the second communication device, and the response message containing the response data stored in the memory in correspondence to the identifier contained in the URL is transmitted when the request message for the URL containing the identifier is received from the first communication device.

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