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    • 42. 发明授权
    • Fixing device and image forming apparatus employing the fixing device
    • 固定装置和采用定影装置的成像装置
    • US08417137B2
    • 2013-04-09
    • US12461314
    • 2009-08-07
    • Yutaka NaitohToshio OgisoTamotsu Ikeda
    • Yutaka NaitohToshio OgisoTamotsu Ikeda
    • G03G15/20
    • G03G15/2039G03G15/2032
    • A fixing device includes a rotary fixing member, a counter member to contact the rotary fixing member, a first heater to heat the rotary fixing member, a driving unit to rotate the rotary fixing member, a temperature detector to detect a temperature of the rotary fixing member, and a contact-and-separation unit to switch between contact and separation states of the rotary fixing member relative to the counter member. In a temperature-raising operation, the driving unit causes the rotary fixing member to rotate when the temperature detector detects that the temperature of the rotary fixing member has reached a first setting temperature. The contact-and-separation unit causes the rotary fixing member in rotation and the counter member to contact each other when the temperature detector detects that the temperature of the rotary fixing member has reached a second setting temperature that is higher than the first setting temperature.
    • 定影装置包括旋转固定构件,与旋转固定构件接触的计数构件,用于加热旋转固定构件的第一加热器,旋转定影构件旋转的驱动单元,温度检测器,用于检测旋转固定件的温度 构件和接触分离单元,以在旋转固定构件相对于计数构件的接触和分离状态之间切换。 在升温动作中,当温度检测器检测出旋转固定部件的温度达到第一设定温度时,驱动部使旋转固定部件旋转。 当温度检测器检测到旋转固定件的温度达到高于第一设定温度的第二设定温度时,接触分离单元使旋转固定部件旋转,并且相对部件彼此接触。
    • 45. 发明授权
    • OFDM receiving device and OFDM receiving method
    • OFDM接收装置和OFDM接收方法
    • US07403472B2
    • 2008-07-22
    • US11089810
    • 2005-03-25
    • Takahiro OkadaYoshikazu MiyatoYasunari IkedaTamotsu Ikeda
    • Takahiro OkadaYoshikazu MiyatoYasunari IkedaTamotsu Ikeda
    • H04J11/00
    • H04L27/2656H04L5/023
    • The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.
    • 切换通道所需的时间可以大大减少。 当通过具有OFDM系统的多个信息信道广播信号时,多个信息信道在频率上被多路复用,并且对于所连接的发送集中地进行IFFT调制,而不是独立地对多个信道进行OFDM调制以进行传输。 通过这种安排,提高了频率利用的效率。 根据本发明,为了连接传输的目的,为每个信息信道同步OFDM帧。 然后,OFDM接收机可以切换用于信号接收的信道,保持帧同步信号。
    • 47. 发明授权
    • OFDM demodulator
    • OFDM解调器
    • US07289765B2
    • 2007-10-30
    • US10505793
    • 2003-12-18
    • Takahiro OkadaTamotsu Ikeda
    • Takahiro OkadaTamotsu Ikeda
    • H04Q7/00
    • H04L27/2657H04L27/2605H04L27/2662H04L27/2676H04L2027/0036
    • An OFDM demodulator includes an FFT circuit, a phase correction circuit, and a timing synchronization circuit. The timing synchronization circuit includes a symbol-boundary calculation circuit to estimate a symbol-boundary position Nx by filtering the correlation peak of a guard interval, symbol-boundary correction circuit to calculate a clock-phase error based on the symbol-boundary position Nx, and a start-flag generation circuit to generate a start flag for the FFT calculation. The symbol-boundary correction circuit subtracts only a value whose precision is smaller than the cycle of a reference clock from the symbol-boundary position Nx, and generates a phase correction signal for each sub-carrier based on the value. The phase correction circuit performs a complex multiplication of the FFF-calculated signal by the phase correction signal to correct the clock-phase error.
    • OFDM解调器包括FFT电路,相位校正电路和定时同步电路。 定时同步电路包括符号边界计算电路,用于通过对保护间隔的相关峰值进行滤波来估计符号边界位置Nx,符号边界校正电路用于基于符号边界位置Nx来计算时钟相位误差, 以及开始标志生成电路,用于生成用于FFT计算的开始标志。 符号边界校正电路仅从符号边界位置Nx仅减去精度小于参考时钟的周期的值,并且基于该值生成每个子载波的相位校正信号。 相位校正电路通过相位校正信号执行FFF计算的信号的复数乘法以校正时钟相位误差。
    • 48. 发明申请
    • Ofdm demodulation device
    • Ofdm解调装置
    • US20050163094A1
    • 2005-07-28
    • US10505793
    • 2003-12-18
    • Takahiro OkadaTamotsu Ikeda
    • Takahiro OkadaTamotsu Ikeda
    • H04J11/00H04J1/00H04L27/00H04L27/26
    • H04L27/2657H04L27/2605H04L27/2662H04L27/2676H04L2027/0036
    • An OFDM demodulator includes an FFT circuit, a phase correction circuit, and a timing synchronization circuit. The timing synchronization circuit includes a symbol-boundary calculation circuit to estimate a symbol-boundary position Nx by filtering the correlation peak of a guard interval, symbol-boundary correction circuit to calculate a clock-phase error based on the symbol-boundary position Nx, and a start-flag generation circuit to generate a start flag for the FFT calculation. The symbol-boundary correction circuit subtracts only a value whose precision is smaller than the cycle of a reference clock from the symbol-boundary position Nx, and generates a phase correction signal for each sub-carrier based on the value. The phase correction circuit performs a complex multiplication of the FFF-calculated signal by the phase correction signal to correct the clock-phase error.
    • OFDM解调器包括FFT电路,相位校正电路和定时同步电路。 定时同步电路包括符号边界计算电路,用于通过对保护间隔的相关峰值进行滤波来估计符号边界位置Nx,符号边界校正电路基于符号边界位置Nx来计算时钟相位误差, 以及开始标志生成电路,用于生成用于FFT计算的开始标志。 符号边界校正电路仅从符号边界位置Nx仅减去精度小于参考时钟的周期的值,并且基于该值生成每个子载波的相位校正信号。 相位校正电路通过相位校正信号执行FFF计算的信号的复数乘法以校正时钟相位误差。
    • 49. 发明授权
    • Apparatus and method for receiving data with bit insertion
    • 用于插入数据的装置和方法
    • US06381727B1
    • 2002-04-30
    • US09588303
    • 2000-06-06
    • Tamotsu Ikeda
    • Tamotsu Ikeda
    • H03M1341
    • H04L1/0068H04L1/0054H04L1/0059H04L1/0071
    • A receiver for data encoded as a series of symbols, each including a plurality of components such as the I and Q components of 16-QAM symbols or other multi-value multi-phase system. Each component denotes values for a plurality of bits. Probability calculation circuits 111-1 through 111-16 use the values of the components constituting each received symbol to calculate the probability that each one of the possible symbols was transmitted and received. Metric calculation circuits 112-1 through 112-4 calculate a bit metric for each bit denoted by the symbol. The bit metric represents the probability that the bit having a specified value was transmitted. The bit metric may be calculated by adding the probabilities calculated by the probability calculation for those possible symbols having a component denoting the specified value of the bit. For example, the sum of the probabilities of all symbols denoting a first bit value of zero gives the probability that a zero bit value was transmitted and received. The data represented by the symbols may represent data encoded by a convolutional code, and the bit metrics may be supplied to a decoder such as a Viterbi decoder.
    • 用于被编码为一系列符号的数据的接收机,每个符号包括诸如16-QAM符号的I和Q分量或其他多值多相系统的多个分量。 每个分量表示多个比特的值。 概率计算电路111-1至111-16使用构成每个接收符号的分量的值来计算发送和接收每个可能符号的概率。 度量计算电路112-1至112-4计算由符号表示的每个位的比特度量。 比特度量表示发送具有指定值的比特的概率。 比特度量可以通过将对于具有表示比特的指定值的分量的那些可能符号的概率计算所计算的概率相加来计算。 例如,表示第一位值为零的所有符号的概率之和给出发送和接收零位值的概率。 由符号表示的数据可以表示由卷积码编码的数据,并且比特度量可以被提供给诸如维特比解码器的解码器。
    • 50. 发明授权
    • Apparatus and method for receiving data with bit insertion
    • 用于插入数据的装置和方法
    • US06324224B1
    • 2001-11-27
    • US08920318
    • 1997-08-27
    • Tamotsu Ikeda
    • Tamotsu Ikeda
    • H03D100
    • H04L1/0068H03M13/00H03M13/23H04L1/0054
    • A message is encoded in a punctured convolutional code by an encoding process involving bit erasure and transmitted in a multi-component modulation system such as 16-QAM in which each component of a signal denotes values for more than one bit. At the receiver, a bit metric calculation circuit calculates a bit metric for each bit of data denoted by each received signal. The resulting sequences of bit metrics undergo bit insertion processing to yield one or more augmented sequences of bit metrics corresponding to the encoded message before bit erasure. The one or more augmented sequences of bit metrics are subjected to most-likelihood decoding scheme such as Viterbi decoding.
    • 通过涉及位擦除的编码处理将消息编码在穿孔卷积码中,并在诸如16-QAM的多分量调制系统中发送,其中信号的每个分量表示超过一个比特的值。 在接收机处,比特度量计算电路针对由每个接收信号表示的每个数据位计算比特度量。 所得到的比特度量序列经历比特插入处理,以在比特删除之前产生与编码消息相对应的比特度量的一个或多个增强序列。 比特度量的一个或多个增强序列经受诸如维特比解码之类的最可能的解码方案。