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    • 45. 发明授权
    • Packet switch and switching method for switching variable length packets
    • 用于切换可变长度分组的分组交换和切换方法
    • US06570876B1
    • 2003-05-27
    • US09280980
    • 1999-03-30
    • Takeshi Aimoto
    • Takeshi Aimoto
    • H04L1256
    • H04L47/528H04L47/10H04L47/2441H04L47/50H04L47/521H04L47/525H04L49/205H04L49/3009H04L49/3027H04L49/90H04L49/9063
    • A packet switch for switching variable length packets, wherein each of output port interfaces includes a buffer memory for storing transmission packets, a transmission priority controller for classifying, based on a predetermined algorithm, transmission packets passed from a packet switching unit into a plurality of queue groups to which individual bandwidths are assigned respectively, and queuing said transmission packets in said buffer memory so as to form a plurality of queues according to transmission priority in each of said queue groups, and a packet read-out controller for reading out said transmission packets from each of said queue groups in the buffer memory according to the order of transmission priority of the packets while guaranteeing the bandwidth assigned to the queue group.
    • 一种用于切换可变长度分组的分组交换机,其中每个输出端口接口包括用于存储传输分组的缓冲存储器,传输优先级控制器,用于基于预定算法将从分组交换单元传递到多个队列中的传输分组 分组分配各个带宽,并且将所述传输分组排队在所述缓冲存储器中,以便根据每个所述队列组中的传输优先级形成多个队列;以及分组读出控制器,用于读出所述传输分组 根据分组的传输优先级的顺序,从缓冲存储器中的每个所述队列组中确定分配给队列组的带宽。
    • 47. 发明授权
    • Excessive flow detection device, excessive flow detection circuit, terminal apparatus and network node
    • 流量检测装置过多,流量检测电路过大,终端设备和网络节点
    • US07953007B2
    • 2011-05-31
    • US12022436
    • 2008-01-30
    • Takeshi AimotoYoshinori Watanabe
    • Takeshi AimotoYoshinori Watanabe
    • H04L12/56
    • H04L47/10H04L45/00H04L47/22H04L47/2441H04L47/36
    • A packet information extraction circuit derives predetermined key information (for example, destination information or transmission source information) from a received packet. A HASH result computation circuit generates m (a plurality of) pseudo-random numbers (HASH results) of fixed length from the derived information. A cache table holds the key information and cumulative packet lengths within a predetermined time period by using the generated pseudo-random numbers as addresses. When a threshold value holding and comparing circuit senses that the cumulative packet length has exceeded a value held therein, it sends a notification signal to judgment means disposed in a packet exchange system. The key information items and the cumulative values of the packet lengths are stored in the cache table on the basis of the received packets in such a way that larger cumulative packet lengths are left behind, whereas smaller cumulative packet lengths are erased.
    • 分组信息提取电路从接收到的分组中导出预定的密钥信息(例如,目的地信息或发送源信息)。 HASH结果计算电路从导出信息生成固定长度的m(多个)伪随机数(HASH结果)。 高速缓存表通过使用生成的伪随机数作为地址在预定时间段内保存密钥信息和累积分组长度。 当阈值保持和比较电路感测到累积分组长度已经超过其中保持的值时,它向设置在分组交换系统中的判断装置发送通知信号。 密钥信息项和分组长度的累积值基于接收到的分组被存储在高速缓存表中,使得较大的累积分组长度被丢弃,而较小的累积分组长度被擦除。
    • 50. 发明申请
    • EXCESSIVE FLOW DETECTION DEVICE, EXCESSIVE FLOW DETECTION CIRCUIT, TERMINAL APPARATUS AND NETWORK NODE
    • 过流检测装置,过流检测电路,端子装置和网络节点
    • US20090022053A1
    • 2009-01-22
    • US12022436
    • 2008-01-30
    • Takeshi AimotoYoshinori Watanabe
    • Takeshi AimotoYoshinori Watanabe
    • H04L12/24H04L12/56
    • H04L47/10H04L45/00H04L47/22H04L47/2441H04L47/36
    • A packet information extraction circuit derives predetermined key information (for example, destination information or transmission source information) from a received packet. A HASH result computation circuit generates m (a plurality of) pseudo-random numbers (HASH results) of fixed length from the derived information. A cache table holds the key information and cumulative packet lengths within a predetermined time period by using the generated pseudo-random numbers as addresses. When a threshold value holding and comparing circuit senses that the cumulative packet length has exceeded a value held therein, it sends a notification signal to judgment means disposed in a packet exchange system. The key information items and the cumulative values of the packet lengths are stored in the cache table on the basis of the received packets in such a way that larger cumulative packet lengths are left behind, whereas smaller cumulative packet lengths are erased.
    • 分组信息提取电路从接收到的分组中导出预定的密钥信息(例如,目的地信息或发送源信息)。 HASH结果计算电路从导出信息生成固定长度的m(多个)伪随机数(HASH结果)。 高速缓存表通过使用生成的伪随机数作为地址在预定时间段内保存密钥信息和累积分组长度。 当阈值保持和比较电路感测到累积分组长度已经超过其中保持的值时,它向设置在分组交换系统中的判断装置发送通知信号。 密钥信息项和分组长度的累积值基于接收到的分组被存储在高速缓存表中,使得较大的累积分组长度被丢弃,而较小的累积分组长度被擦除。