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41. 发明申请

US20050024084A1 Semiconductor integrated circuit and signal sending/receiving system 审中-公开
标题翻译：半导体集成电路和信号发送/接收系统
公开(公告)号：US20050024084A1
公开(公告)日：2005-02-03
申请号：US10855351
申请日：2004-05-28
申请人： Takashi Hirata , Toru Iwata
发明人： Takashi Hirata , Toru Iwata
IPC分类号： G05F1/56 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0278 , G05F1/56 , H04L25/028 , H04L25/0292
摘要： A terminal resistor built in a signal-sending or signal-receiving semiconductor integrated circuit is composed of a parallel circuit of a polysilicon resistor element having excellent frequency characteristic and a P-type MOS transistor. The resistance value of the polysilicon resistor element is set so as to be an approximate value of the characteristic impedance of a transmission line to be connected. The gate voltage of the P-type MOS transistor is controlled by a gate bias voltage adjustment circuit. The resistance value of the P-type MOS transistor is variably adjusted. Variation in the resistance value of the polysilicon resistor element due to dispersion in its manufacturing process is absorbed by variably adjusting the resistance value of the P-type MOS transistor. The combined resistance value of the polysilicon resistor element and the P-type MOS transistor is adjusted with high precision just to the characteristic impedance of the transmission line. Thus, a signal-sending or signal-receiving semiconductor integrated circuit in which the terminal resistor having excellent frequency and DC characteristics is built can be obtained.
摘要翻译：内置在信号发送或信号接收半导体集成电路中的端子电阻由具有优异频率特性的多晶硅电阻元件和P型MOS晶体管的并联电路组成。将多晶硅电阻元件的电阻值设定为要连接的传输线的特性阻抗的近似值。 P型MOS晶体管的栅极电压由栅极偏置电压调节电路控制。可变地调节P型MOS晶体管的电阻值。通过可变地调节P型MOS晶体管的电阻值来吸收由于其制造过程中的分散而导致的多晶硅电阻元件的电阻值的变化。与传输线的特性阻抗相比，多晶硅电阻元件和P型MOS晶体管的组合电阻值被高精度地调整。因此，可以获得其中构建具有优异的频率和DC特性的端子电阻器的信号发送或信号接收半导体集成电路。

42. 发明授权

US06794912B2 Multi-phase clock transmission circuit and method 失效
标题翻译：多相时钟传输电路及方法
公开(公告)号：US06794912B2
公开(公告)日：2004-09-21
申请号：US10361610
申请日：2003-02-11
申请人： Takashi Hirata , Toru Iwata
发明人： Takashi Hirata , Toru Iwata
IPC分类号： H03D324
CPC分类号： H03L7/0805 , H03K5/133 , H03K5/1504 , H03L7/07 , H03L7/08 , H03L7/0812 , H03L7/0814
摘要： A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.
摘要翻译：多相时钟传输电路包括：时钟发生器，用于响应于参考时钟和所产生的时钟之间的相位差，产生与参考时钟同步的时钟和控制信号; 以及用于基于时钟和控制信号产生多相时钟的延迟电路。时钟发生器产生具有等于参考时钟的频率的整数倍的频率的信号，并将该信号作为时钟输出。延迟电路具有接收时钟并且包括多个级联连接的延迟元件的电路，每个延迟元件根据与输入信号的控制信号给出延迟。将从多个延迟元件输出的信号用作构成多相时钟的信号。

43. 发明授权

US06297675B1 Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
标题翻译：具有串行可互连数据总线的半导体集成电路和半导体集成电路系统
公开(公告)号：US06297675B1
公开(公告)日：2001-10-02
申请号：US09478530
申请日：2000-01-06
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
IPC分类号： H03B100
CPC分类号： H03K19/018514 , Y10T307/549
摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.
摘要翻译：在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。第一芯片包括输出电路和用于控制输出电路的控制器。第二芯片包括输入电路。例如，输出电路将电流从电源提供给数据线之一。然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。随后，输出电路将反馈的直流电流提供给选通线之一。作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。然后将反馈电流排到地面。因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

44. 发明授权

US06215192B1 Integrated circuit package and integrated circuit package control system 失效
标题翻译：集成电路封装和集成电路封装控制系统
公开(公告)号：US06215192B1
公开(公告)日：2001-04-10
申请号：US09095211
申请日：1998-06-10
申请人： Takashi Hirata , Hironori Akamatsu
发明人： Takashi Hirata , Hironori Akamatsu
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/06136 , H01L2224/16145 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/48624 , H01L2224/48724 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2225/06562 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The integrated circuit package of this invention includes a first integrated circuit chip and a second integrated circuit chip having a same function, wherein the first integrated circuit chip and the second integrated circuit chip are connected to a common bus.
摘要翻译：本发明的集成电路封装包括具有相同功能的第一集成电路芯片和第二集成电路芯片，其中第一集成电路芯片和第二集成电路芯片连接到公共总线。

45. 发明授权

US06201412B1 Semiconductor integrated circuit with driver stabilization using parasitic capacitance 失效
标题翻译：具有驱动器稳定的半导体集成电路使用寄生电容
公开(公告)号：US06201412B1
公开(公告)日：2001-03-13
申请号：US09123902
申请日：1998-07-28
申请人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
发明人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
IPC分类号： H03K190175
CPC分类号： H03K19/01707
摘要： The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.
摘要翻译：本发明的半导体集成电路包括：驱动器，其包括用于驱动负载的MOS晶体管; 以及用于稳定由于MOS晶体管的栅极 - 源极寄生电容而在MOS晶体管的源极处的电压变化的稳定器。

46. 发明授权

US6073245A Skewing-suppressive output buffer circuit 有权
标题翻译：偏移抑制输出缓冲电路
公开(公告)号：US6073245A
公开(公告)日：2000-06-06
申请号：US234708
申请日：1999-01-21
申请人： Takashi Hirata , Toru Iwata
发明人： Takashi Hirata , Toru Iwata
IPC分类号： G06F5/06 , G06F1/12
CPC分类号： G06F5/06
摘要： In an output buffer circuit, an input signal is transmitted through a bus by way of a latch circuit and a driver. A stable-state interval detector detects an interval during which the input signal remains in the same logical state. If the stable-state interval detected is relatively short, a drivability controller controls the drivability of the driver at a normal value. To the contrary, if the interval detected is relatively long, the controller increases the drivability of the driver. In general, if the stable-state interval of an input signal is relatively long, then the time taken for the subsequent logical state transition of the signal tends to be longer as compared with a signal having a shorter stable-state interval. However, if the drivability of the driver is increased, then the state transition time is shortened, and substantially equalized with that of a signal having a relatively short stable-state interval. As a result, signal skewing can be minimized.
摘要翻译：在输出缓冲电路中，输入信号通过一个总线通过一个锁存电路和一个驱动器传输。稳态区间检测器检测输入信号保持在相同逻辑状态的间隔。如果检测到的稳态间隔相对较短，则驾驶员控制器将驾驶员的驾驶性能控制在正常值。相反，如果检测到的间隔相对较长，则控制器增加驾驶员的驾驶性能。一般来说，如果输入信号的稳态间隔相对较长，则与具有较短稳态间隔的信号相比，信号的后续逻辑状态转换所花费的时间趋于变长。然而，如果驾驶员的驾驶性能增加，则状态转移时间缩短，并且与具有相对较短的稳态间隔的信号基本相等。结果，信号偏移可以最小化。

47. 发明授权

US5771826A Memory card storing embroidery data and embroidery sewing device for use with memory card 失效
标题翻译：存储卡存储刺绣数据和刺绣缝纫设备，用于存储卡
公开(公告)号：US5771826A
公开(公告)日：1998-06-30
申请号：US742836
申请日：1996-10-31
申请人： Takashi Hirata
发明人： Takashi Hirata
IPC分类号： D05B19/08 , D05B19/06 , D05B19/10 , D05C5/06 , G05B19/408 , D05B21/00 , D05C5/04
CPC分类号： G05B19/408 , D05B19/06 , D05B19/105
摘要： An embroidery sewing memory card including a first storage region storing sets of pattern data under corresponding lead addresses, each set of pattern data corresponding to an embroidery pattern and usable in at least one of a plurality of embroidery sewing machine types; and a second storage region storing data in table form indicating correspondence between the embroidery sewing machine types and the lead addresses of pattern data based on which pattern data is usable in which embroidery sewing machine type.
摘要翻译：一种刺绣缝制存储卡，包括：第一存储区域，存储相应引线地址下的图案数据集;每组图案数据对应于刺绣图案，并可用于多种刺绣缝纫机类型中的至少一种; 以及第二存储区域，其以表格形式指示刺绣缝纫机类型和刺绣缝纫机类型之间的对应关系的图形数据的引导地址。

48. 外观设计

USD265992S Acoustic coupler 失效
公开(公告)号：USD265992S
公开(公告)日：1982-08-31
申请号：US82910
申请日：1979-10-09
申请人： Takashi Hirata , Kunio Hirose
设计人： Takashi Hirata , Kunio Hirose

49. 外观设计

USD263151S Desk top electronic calculator 失效
公开(公告)号：USD263151S
公开(公告)日：1982-02-23
申请号：US126354
申请日：1980-03-03
申请人： Takashi Hirata , Takashi Yomo , Junichi Motoyoshi
设计人： Takashi Hirata , Takashi Yomo , Junichi Motoyoshi

50. 发明授权

US08953080B2 Image display apparatus and image display method for switching a display mode 有权
标题翻译：用于切换显示模式的图像显示装置和图像显示方法
公开(公告)号：US08953080B2
公开(公告)日：2015-02-10
申请号：US12905481
申请日：2010-10-15
申请人： Takashi Hirata
发明人： Takashi Hirata
IPC分类号： H04N5/232 , H04N5/228
CPC分类号： H04N5/23293 , H04N5/23219 , H04N5/23245
摘要： A display apparatus of the present invention includes a reception unit configured to receive an image captured by an imaging apparatus from the imaging apparatus and a switching unit configured to switch the display mode of the captured image to a single shooting display mode for displaying the image captured by the imaging apparatus in the single shooting mode or a continuous shooting display mode for displaying the image captured by the imaging apparatus in the continuous shooting mode based on an interval at which the captured image is received by the reception unit.
摘要翻译：本发明的显示装置包括：接收单元，被配置为从成像装置接收由成像装置拍摄的图像;以及切换单元，被配置为将拍摄图像的显示模式切换到单次拍摄显示模式，以显示拍摄的图像通过成像装置以单次拍摄模式或连续拍摄显示模式，用于基于由接收单元接收到拍摄图像的间隔，以连续拍摄模式显示由成像装置拍摄的图像。

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