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    • 44. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US08274815B2
    • 2012-09-25
    • US12886931
    • 2010-09-21
    • Reika IchiharaTakayuki Tsukamoto
    • Reika IchiharaTakayuki Tsukamoto
    • G11C11/00
    • G11C11/00G11C2013/0083
    • A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
    • 根据实施例的非易失性半导体存储器件包括多个第一,第二线,多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处,并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外,控制电路在设定操作期间向可变电阻施加第二脉冲电压,第二脉冲电压具有与第一脉冲电压相反的极性。 此外,控制电路在复位操作期间向可变电阻器施加第三脉冲电压,第三脉冲电压具有与第一脉冲电压相同的极性。