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41. 发明申请

US20060163730A1 Electronic device and its manufacturing method 审中-公开
标题翻译：电子器件及其制造方法
公开(公告)号：US20060163730A1
公开(公告)日：2006-07-27
申请号：US10520816
申请日：2004-04-07
申请人： Susumu Matsumoto , Mitsuru Sekiguchi , Yasutaka Nishioka , Kazuo Tomita , Akihisa Iwasaki , Keiji Hashimoto
发明人： Susumu Matsumoto , Mitsuru Sekiguchi , Yasutaka Nishioka , Kazuo Tomita , Akihisa Iwasaki , Keiji Hashimoto
IPC分类号： H01L23/52
CPC分类号： H01L21/76801 , H01L21/02126 , H01L21/0214 , H01L21/02164 , H01L21/02167 , H01L21/02203 , H01L21/02274 , H01L21/0274 , H01L21/3144 , H01L21/76802 , H01L21/76808 , H01L21/76829 , H01L21/76835
摘要： A first nitrogen-containing insulating film is formed under a low dielectric constant film, in which a via hole is formed, with a first nitrogen-non-containing insulating film interposed between the first nitrogen-containing insulating film and the low dielectric constant film. A second nitrogen-containing insulating film is formed over the low dielectric constant film with a second nitrogen-non-containing insulating film interposed therebetween.
摘要翻译：在第一含氮绝缘膜和低介电常数膜之间插入第一含氮不含绝缘膜的低介电常数膜形成第一含氮绝缘膜，其中形成通孔。在低介电常数膜上形成第二含氮绝缘膜，其间插入第二含氮不含绝缘膜。

42. 发明授权

US06185086B2 Capacitor 失效
标题翻译：电容器
公开(公告)号：US06185086B2
公开(公告)日：2001-02-06
申请号：US09203766
申请日：1998-12-02
申请人： Yutaka Tanaka , Katsumasa Kaneko , Susumu Matsumoto
发明人： Yutaka Tanaka , Katsumasa Kaneko , Susumu Matsumoto
IPC分类号： H01G220
CPC分类号： H01G4/236 , H01G4/228
摘要： A capacitor element having a terminal, an electric insulating material installed to cover the capacitor element, a wire connected to the terminal, and a reinforcing structure installed at the junction for connecting the terminal and the wire. In this constitution, the junction of the terminals and wires maintains mechanical strength and electrical insulation and is enhanced in reliability for a long period against mechanical stress or vibration to the capacitor from outside. Still more, invasion of moisture or dust into the capacitor can be prevented. As a result, the life of the excellent mechanical strength and electrical insulation is enhanced, and the capacitor having a stable reliability for a long time may be obtained.
摘要翻译：具有端子的电容器元件，安装用于覆盖电容器元件的电绝缘材料，连接到端子的电线以及安装在用于连接端子和电线的连接处的加强结构。在这种结构中，端子和电线的接合部保持机械强度和电绝缘性，并且长时间地提高了机械应力或从外部向电容器的振动的可靠性。此外，可以防止水分或灰尘侵入电容器。结果，提高了优异的机械强度和电绝缘性的寿命，并且可以获得长时间具有稳定的可靠性的电容器。

43. 发明授权

US5399890A Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level 失效
标题翻译：半导体存储器件，其中存储单元的电容器电极和外围电路的互连层形成在一个级中
公开(公告)号：US5399890A
公开(公告)日：1995-03-21
申请号：US257955
申请日：1994-06-10
申请人： Shozo Okada , Hisashi Ogawa , Naoto Matsuo , Yoshiro Nakata , Toshiki Yabu , Susumu Matsumoto
发明人： Shozo Okada , Hisashi Ogawa , Naoto Matsuo , Yoshiro Nakata , Toshiki Yabu , Susumu Matsumoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.
摘要翻译：本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个位于层叠电容器和第一级互连层之上的第二级互连层。多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。第二电极层连接到多个第二级互连层之一的一部分。多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。

44. 发明授权

US5300814A Semiconductor device having a semiconductor substrate with reduced step between memory cells 失效
标题翻译：半导体器件具有在存储单元之间具有减小的步骤的半导体衬底
公开(公告)号：US5300814A
公开(公告)日：1994-04-05
申请号：US915898
申请日：1992-07-17
申请人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
发明人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/10 , H01L27/105 , H01L27/108 , H01L23/48 , H01L29/46
CPC分类号： H01L27/105 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S257/92
摘要： A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.
摘要翻译：一种半导体器件，包括半导体衬底，多个存储单元区域，每个存储单元区域具有设置在半导体衬底上的多个存储单元，形成在半导体衬底上方的第一级中的字线，形成在第二级上方的位线第一级和背衬线，其具有比字线更低的电阻并且形成在高于第二级的第三级中。在存储单元区域外部的第二电平中形成虚拟位线，以便减小形成在存储单元区域周边的台阶。虚拟位线也用于互连字线和背衬线，使得它们之间的电连接稳定。

45. 发明授权

US5222016A Frequency converter 失效
标题翻译：频率转换器
公开(公告)号：US5222016A
公开(公告)日：1993-06-22
申请号：US688611
申请日：1991-07-29
申请人： Susumu Matsumoto , Masaru Hashimoto
发明人： Susumu Matsumoto , Masaru Hashimoto
IPC分类号： H03D7/12
CPC分类号： H03D7/12
摘要： According to this invention, a frequency converter comprises a frequency mixer (11) formed in a semiconductor integrated circuit (10), an impedance conversion/signal amplitude limit differential amplifier (12) formed in the semiconductor integrated circuit and connected to the output of the frequency mixer, a first frequency mixing output terminal (14) connected to an output terminal of the frequency mixer and serving as an external terminal of the semiconductor integrated circuit, and a second frequency mixing output terminal (15) connected to an output terminal of the differential amplifier and serving as an external terminal of the semiconductor integrated circuit.
摘要翻译： PCT No.PCT / JP90 / 01302 Sec。 371日期1991年7月29日根据本发明，一种变频器包括形成在半导体集成电路（10）中的混频器（11），阻抗转换/信号振幅限制（10）差分放大器（12），其形成在所述半导体集成电路中并连接到所述混频器的输出;第一混频输出端（14），连接到所述混频器的输出端并用作所述半导体集成电路的外部端，以及连接到差分放大器的输出端并用作半导体集成电路的外部端子的第二混频输出端子（15）。

46. 发明授权

US5217914A Method for making semiconductor integration circuit with stacked capacitor cells 失效
标题翻译：具有层叠电容器单元的半导体积分电路的方法
公开(公告)号：US5217914A
公开(公告)日：1993-06-08
申请号：US683603
申请日：1991-04-10
申请人： Susumu Matsumoto , Toshiki Yabu , Yoshiro Nakata , Naoto Matsuo , Shozo Okada , Hiroyuki Sakai
发明人： Susumu Matsumoto , Toshiki Yabu , Yoshiro Nakata , Naoto Matsuo , Shozo Okada , Hiroyuki Sakai
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/91
摘要： Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.
摘要翻译：公开了具有层叠电容器单元的半导体积分电路。每个单元包括用于存储电荷的电荷存储电极，以及集成在其上的电容器绝缘膜和相对的平板电极。电荷存储电极基本上由至少双框状部分或至少一个柱状部分中的底部和部分组成，以及围绕从底面向上升起的柱状部分的至少一个框状部分。电容器沉积膜由沉积在电荷存储电极的所有底面和所有表面上的介电材料膜构成，并与相对的板电极配合构建电容器。所述制造叠层电容器电池的方法可以通过重复氧化膜和导电膜的沉积以及各向异性蚀刻来形成自对准电容器。

47. 外观设计

USD328196S High chair 失效
公开(公告)号：USD328196S
公开(公告)日：1992-07-28
申请号：US365146
申请日：1989-05-31
申请人： Takehiko Takahashi , Yoshiyasu Ishii , Susumu Matsumoto
设计人： Takehiko Takahashi , Yoshiyasu Ishii , Susumu Matsumoto

48. 外观设计

USD307629S Auxiliary toilet seat for a child 失效
公开(公告)号：USD307629S
公开(公告)日：1990-05-01
申请号：US134473
申请日：1987-12-16
申请人： Takehiko Takahashi , Yoshiyasu Ishii , Susumu Matsumoto , Jun Sekine
设计人： Takehiko Takahashi , Yoshiyasu Ishii , Susumu Matsumoto , Jun Sekine

49. 外观设计

USD291156S Convertible high chair 失效
公开(公告)号：USD291156S
公开(公告)日：1987-08-04
申请号：US670848
申请日：1984-11-13
申请人： Shinroku Nakao , Yoshiyasu Ishii , Susumu Matsumoto
设计人： Shinroku Nakao , Yoshiyasu Ishii , Susumu Matsumoto

50. 外观设计

USD282673S Toy rattle 失效
公开(公告)号：USD282673S
公开(公告)日：1986-02-18
申请号：US552600
申请日：1983-11-16
申请人： Shinroku Nakao , Yoshiyasu Ishii , Susumu Matsumoto
设计人： Shinroku Nakao , Yoshiyasu Ishii , Susumu Matsumoto

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