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41. 发明授权

US07557033B2 Method of forming metal line of semiconductor memory device 失效
标题翻译：形成半导体存储器件金属线的方法
公开(公告)号：US07557033B2
公开(公告)日：2009-07-07
申请号：US11647087
申请日：2006-12-27
申请人： Eun Soo Kim , Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim
发明人： Eun Soo Kim , Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/32139 , H01L21/76837
摘要： A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.
摘要翻译：形成半导体存储器件的金属线的方法包括以下步骤：在半导体衬底上的第一层间绝缘层中形成镶嵌结构的插塞，在其上形成阻挡金属层，金属层和抗反射层根据特定图案蚀刻抗反射层，金属层和阻挡金属层，并在金属层的侧壁上形成绝缘层。

42. 发明申请

US20090053889A1 METHOD FOR FORMING A METAL LINE IN A SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US20090053889A1
公开(公告)日：2009-02-26
申请号：US12053488
申请日：2008-03-21
申请人： Seung Hee Hong , Jung Geun Kim , Eun Soo Kim
发明人： Seung Hee Hong , Jung Geun Kim , Eun Soo Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes contact plugs formed in contact holes defined in an interlayer dielectric. Upper portions of the contact plugs are etched. A first barrier layer is formed on a surface of the interlayer dielectric including the contact plugs. A second barrier layer is formed on the first barrier layer over the interlayer dielectric. The second barrier layer has lower compatibility with a metallic material than the first barrier layer. A first metal layer is formed over the first and second barrier layers. The first metal layer, the first barrier layer and the second barrier layer are then patterned.
摘要翻译：半导体器件包括形成在层间电介质中限定的接触孔中的接触塞。接触塞的上部被蚀刻。在包括接触塞的层间电介质的表面上形成第一阻挡层。在层间电介质上的第一阻挡层上形成第二阻挡层。与第一阻挡层相比，第二阻挡层与金属材料的相容性较低。在第一和第二阻挡层上形成第一金属层。然后对第一金属层，第一阻挡层和第二阻挡层进行图案化。

43. 发明申请

US20080160753A1 Method of forming metal wire in semiconductor device 有权
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US20080160753A1
公开(公告)日：2008-07-03
申请号：US11801498
申请日：2007-05-10
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76882 , H01L23/53223 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the barrier metal layer, and filling the dual damascene pattern with a conductive material to form a metal wire.
摘要翻译：公开了一种在半导体器件中形成金属线的方法。该方法包括以下步骤：蚀刻在半导体衬底上形成的绝缘层，以形成双镶嵌图案，在双镶嵌图案中形成阻挡金属层，形成金属层在阻挡金属层上，并用导电材料填充双镶嵌图案以形成金属线。

44. 发明申请

US20080146023A1 METHOD OF FORMING METAL WIRE IN SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US20080146023A1
公开(公告)日：2008-06-19
申请号：US11753543
申请日：2007-05-24
申请人： Seung Hee HONG , Cheol Mo Jeong , Jung Geun Kim , Eun Soo Kim
发明人： Seung Hee HONG , Cheol Mo Jeong , Jung Geun Kim , Eun Soo Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/28562 , H01L21/32131 , H01L21/76879 , H01L21/76882
摘要： A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.
摘要翻译：在半导体器件中形成金属线的方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻工艺以形成沟槽和绝缘层图案，绝缘层图案限定沟槽。在绝缘层图案和沟槽之上形成阻挡金属层。在阻挡金属层上进行第二蚀刻工艺以暴露沟槽的上角，同时留下基本上被阻挡金属层覆盖的沟槽。在沟槽中的阻挡金属层的上方形成有金属层。进行用于回流金属层的热处理工艺。金属层被平坦化。

45. 发明申请

US20080081453A1 Method of forming metal wire of semiconductor device 审中-公开
标题翻译：形成半导体器件金属线的方法
公开(公告)号：US20080081453A1
公开(公告)日：2008-04-03
申请号：US11603752
申请日：2006-11-22
申请人： Jung Geun Kim , Cheol Mo Jeong , Eun Soo Kim , Seung Hee Hong
发明人： Jung Geun Kim , Cheol Mo Jeong , Eun Soo Kim , Seung Hee Hong
IPC分类号： H01L21/44
CPC分类号： H01L21/76831 , H01L21/76843 , H01L21/76876 , H01L21/7688
摘要： A method of forming a metal line of a semiconductor device includes the steps of forming an insulating layer and a glue layer on a semiconductor substrate, removing a portion of the glue layer and the insulating layer to form trenches, forming a metal layer over the semiconductor substrate including the trenches and the glue layer, and performing a polishing process until the insulating layer is exposed, thus forming a metal line.
摘要翻译：形成半导体器件的金属线的方法包括以下步骤：在半导体衬底上形成绝缘层和胶层，去除一部分胶层和绝缘层以形成沟槽，在半导体上形成金属层包括沟槽和胶层的衬底，并且进行抛光工艺直到绝缘层露出，从而形成金属线。

46. 发明申请

US20080003814A1 Method of forming metal line of semiconductor memory device 失效
标题翻译：形成半导体存储器件金属线的方法
公开(公告)号：US20080003814A1
公开(公告)日：2008-01-03
申请号：US11647087
申请日：2006-12-27
申请人： Eun Soo Kim , Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim
发明人： Eun Soo Kim , Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/32139 , H01L21/76837
摘要： A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.
摘要翻译：形成半导体存储器件的金属线的方法包括以下步骤：在半导体衬底上的第一层间绝缘层中形成镶嵌结构的插塞，在其上形成阻挡金属层，金属层和抗反射层根据特定图案蚀刻抗反射层，金属层和阻挡金属层，并在金属层的侧壁上形成绝缘层。

47. 发明申请

US20080003796A1 METHOD OF FORMING BIT LINE OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件位线的方法
公开(公告)号：US20080003796A1
公开(公告)日：2008-01-03
申请号：US11614082
申请日：2006-12-21
申请人： Cheol Mo JEONG , Whee Won Cho , Eun Soo Kim , Seung Hee Hong
发明人： Cheol Mo JEONG , Whee Won Cho , Eun Soo Kim , Seung Hee Hong
IPC分类号： H01L21/44
CPC分类号： H01L21/76864 , H01L21/28562 , H01L21/28568 , H01L21/76846 , H01L21/76876
摘要： A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.
摘要翻译：形成半导体器件的导电结构（例如位线）的方法包括在形成结构的半导体衬底上形成阻挡金属层。在阻挡金属层上形成非晶氮化钛层。在包含硼气体的气氛下，在非晶态氮化钛层上形成钨种子层。在钨籽晶层上形成钨层，形成位线。

48. 发明申请

US20060270212A1 Method of forming bit line of flash memory device 有权
标题翻译：形成闪存器件位线的方法
公开(公告)号：US20060270212A1
公开(公告)日：2006-11-30
申请号：US11439527
申请日：2006-05-22
申请人： Woo Yung Jung , Tae Kyung Kim , Eun Soo Kim
发明人： Woo Yung Jung , Tae Kyung Kim , Eun Soo Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76838 , H01L21/76895 , H01L27/115 , H01L27/11521
摘要： A method for forming a semiconductor device includes forming a plurality of drain contact holes in a first interlayer insulating layer provided over a semiconductor substrate. First metal material having a predetermined thickness is formed over the first interlayer insulating layer, the first metal material filling the drain contact holes. A first metal layer is formed by patterning the first metal material, the first metal layer having a plurality of lines of a first type and a plurality of landing pads. A second interlayer insulating layer is formed over the patterned first metal material. A plurality of trenches is formed in the second interlayer insulating layer, the trenches exposing the landing pads. A second metal layer is formed by providing second metal material over the second interlayer insulating layer and filling the trenches, the second metal layer including a plurality of lines of a second type defined within the trenches, the lines of the second type contacting the landing pads. The first and second metal layers define a first metal level of the semiconductor device. The lines of the first type define odd-number lines of the first metal level, and the lines of the second type define even-number lines of the first metal level.
摘要翻译：一种形成半导体器件的方法包括在设置在半导体衬底上的第一层间绝缘层中形成多个漏极接触孔。在第一层间绝缘层上形成具有预定厚度的第一金属材料，第一金属材料填充漏极接触孔。通过图案化第一金属材料形成第一金属层，第一金属层具有多个第一类型的线和多个着陆焊盘。在图案化的第一金属材料上形成第二层间绝缘层。多个沟槽形成在第二层间绝缘层中，沟槽露出着陆焊盘。第二金属层通过在第二层间绝缘层上提供第二金属材料并填充沟槽而形成，第二金属层包括限定在沟槽内的多条第二类线，第二类线与接地焊盘接触。第一和第二金属层限定半导体器件的第一金属层。第一类型的线限定第一金属级的奇数行，并且第二类型的线限定第一金属级的偶数行。

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