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41. 发明授权

US08510514B2 Apparatus, method and data processing element for efficient parallel processing of multimedia data 有权
标题翻译：用于多媒体数据的高效并行处理的装置，方法和数据处理元件
公开(公告)号：US08510514B2
公开(公告)日：2013-08-13
申请号：US12112156
申请日：2008-04-30
申请人： Young Su Kwon , Bon Tae Koo , Nak Woong Eum
发明人： Young Su Kwon , Bon Tae Koo , Nak Woong Eum
IPC分类号： G06F12/00
CPC分类号： G06F9/544 , G06F12/109 , G06F2212/656
摘要： Provided are an apparatus, a method, and a data processing element (DPE) for efficient parallel processing of multimedia data. The DPE includes: a memory routing unit (MRU) comprising a shared memory page shared by the DPE and DPEs that are adjacent to the DPE, and a shared page switch selectively connecting the shared memory page to the DPE and the adjacent DPEs; and a data processing unit (DPU) comprising a virtual page for connecting the DPU to the shared memory page, and a dynamic remapper assigning the shared memory page to a DPE according to conditions that a series of tasks for processing multimedia data are performed in the DPE and the adjacent DPEs, and controlling the shared page switch according to the assigning. Accordingly, multimedia data can be efficiently processed in parallel by mapping a temporal and directional shared memory between DPEs.
摘要翻译：提供了一种用于多媒体数据的有效并行处理的装置，方法和数据处理元件（DPE）。 DPE包括：存储器路由单元（MRU），包括由与DPE相邻的DPE和DPE共享的共享存储器页面，以及共享页面交换机，其选择性地将共享存储器页面连接到DPE和相邻DPE; 以及包括用于将DPU连接到共享存储器页面的虚拟页面的数据处理单元（DPU），以及动态再映射器，其根据在一系列用于处理多媒体数据的一系列任务在 DPE和相邻DPE，并根据分配来控制共享页面交换机。因此，可以通过在DPE之间映射时间和定向共享存储器来并行地高效地处理多媒体数据。

42. 发明授权

US08311081B2 Frame synchronization method and receiver for communication modem using the same 失效
标题翻译：帧同步方法和接收机用于通信调制解调器使用
公开(公告)号：US08311081B2
公开(公告)日：2012-11-13
申请号：US12629014
申请日：2009-12-01
申请人： Ki Hyuk Park , Bon Tae Koo , Nak Woong Eum
发明人： Ki Hyuk Park , Bon Tae Koo , Nak Woong Eum
IPC分类号： H04B1/707
CPC分类号： H04B1/7075 , H04J3/0608
摘要： Disclosed are a frame synchronization method and a receiver for a communication modem using the same. The frame synchronization method includes performing a correlation operation between a reception data stream and a preamble to output a synchronous signal; and computing correlation values between spreading codes and a reception data stream synchronized with the synchronous signal, wherein a maximum value of the computed correlation values is compared with a preset threshold value, and the outputting of the synchronous signal is performed again when the maximum value is smaller than the preset threshold value.
摘要翻译：公开了一种帧同步方法和使用该帧同步方法的通信调制解调器的接收机。帧同步方法包括执行接收数据流与前同步码之间的相关运算以输出同步信号; 以及计算扩展码与与所述同步信号同步的接收数据流之间的相关值，其中将所计算的相关值的最大值与预设阈值进行比较，并且当所述最大值为小于预设阈值。

43. 发明申请

US20120166682A1 MEMORY MAPPING APPARATUS AND MULTIPROCESSOR SYSTEM ON CHIP PLATFORM INCLUDING THE SAME 审中-公开
标题翻译：芯片平台上的存储映射设备和多处理器系统，包括它们
公开(公告)号：US20120166682A1
公开(公告)日：2012-06-28
申请号：US13307021
申请日：2011-11-30
申请人： June Young CHANG , Nak Woong Eum
发明人： June Young CHANG , Nak Woong Eum
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A memory mapping apparatus includes a core/memory selector adapted to select a core from among a plurality of cores, and select a memory from among a plurality of memories, a transfer path allocator adapted to allocate a data transfer path between the core and memory which are selected by the core/memory selector, and a DMA control signal setter adapted to set a signal to be controlled to a DMA Controller which controls a plurality of DMAs corresponding to data transfer paths between the cores and the memories.
摘要翻译：存储器映射设备包括：核心/存储器选择器，适于从多个核心中选择一个核心，并从多个存储器中选择一个存储器;传输路径分配器，适于在核心和存储器之间分配数据传输路径，由核心/存储器选择器选择，以及DMA控制信号设置器，其适于将要控制的信号设置为控制与核心和存储器之间的数据传送路径相对应的多个DMA的DMA控制器。

44. 发明授权

US07958321B2 Apparatus and method for reducing memory access conflict 有权
标题翻译：减少内存访问冲突的装置和方法
公开(公告)号：US07958321B2
公开(公告)日：2011-06-07
申请号：US12195153
申请日：2008-08-20
申请人： Young Su Kwon , Bon Tae Koo , Nak Woong Eum
发明人： Young Su Kwon , Bon Tae Koo , Nak Woong Eum
IPC分类号： G06F12/06
CPC分类号： G06F12/0607
摘要： Provided are an apparatus and a method of reducing memory access conflict. An apparatus for reducing memory access conflict when a plurality of data processing elements perform simultaneous access to a memory including a plurality of pages, each of which includes a plurality of subpages, the apparatus comprising: an access arbiter mapping a subpage division address corresponding to least significant bits of a memory access address received from each of the data processing elements to another address having a same number of bits as the subpage division address in order for data to be output from each of the subpages in a corresponding page at a time of the simultaneous access; and a selector, prepared for each of the pages, selecting to output one of the data output from the subpages using the mapped results.
摘要翻译：提供了一种减少存储器访问冲突的装置和方法。一种用于当多个数据处理单元同时访问包括多个页面的存储器的存储器访问冲突的装置，每个页面包括多个子页面，所述设备包括：访问仲裁器，映射对应于最小的子页面分割地址从每个数据处理元件接收到的存储器访问地址的有效位到具有与子页地址相同位数的另一地址，以便从数据处理单元中的相应页面中的每个子页面输出数据同时访问; 以及为每个页面准备的选择器，选择使用映射结果输出从子页面输出的数据之一。

45. 发明授权

US07366087B2 Delta-predicted frequency offset compensation apparatus and method thereof 失效
标题翻译： Delta预测频偏补偿装置及其方法
公开(公告)号：US07366087B2
公开(公告)日：2008-04-29
申请号：US10334353
申请日：2002-12-31
申请人： Ju Hyun Lee , Myung Sin Kwark , Nak Woong Eum , Jong Dae Kim
发明人： Ju Hyun Lee , Myung Sin Kwark , Nak Woong Eum , Jong Dae Kim
IPC分类号： H04J11/00 , H03D1/04
CPC分类号： H04L27/2657 , H04L27/2676
摘要： Provided are delta-predicted frequency offset compensation apparatus and method that estimates an offset delta of forthcoming symbols by using a principle that the offset delta of a symbol in a previous section is almost the same as an offset delta of some forthcoming symbols. The offset compensation method of the present research includes the steps of: a) estimating a frequency offset of a communication system based on an estimation period and estimation algorithm; b) outputting a compensation value for offset compensation through a feedback loop by considering the frequency offset value estimated based on the estimation period and the frequency offset delta estimated based on the estimation period and delay interval; and c) shifting the phase of a signal by as much as the offset corresponding to an input signal of the communication system to compensate the symbol for the frequency offset. The apparatus and method of the present invention can be applied to a communication system using an orthogonal frequency division multiplexing.
摘要翻译：提供了德尔福预测的频偏补偿装置和方法，其通过使用前一部分中的符号的偏移增量几乎与一些即将到来的符号的偏移增量几乎相同的原理来估计即将到来的符号的偏移增量。本研究的偏移补偿方法包括以下步骤：a）基于估计周期和估计算法估计通信系统的频偏; b）通过考虑基于估计周期估计的频率偏移值和基于估计周期和延迟间隔估计的频偏增加，通过反馈回路输出偏移补偿补偿值; 以及c）使信号的相位偏移与通信系统的输入信号相对应的偏移量以补偿用于频率偏移的符号。本发明的装置和方法可以应用于使用正交频分复用的通信系统。

46. 发明授权

US08638859B2 Apparatus for decoding residual data based on bit plane and method thereof 失效
标题翻译：用于基于位平面解码残差数据的装置及其方法
公开(公告)号：US08638859B2
公开(公告)日：2014-01-28
申请号：US13226765
申请日：2011-09-07
申请人： Jae-Jin Lee , Kyung Su Kim , Jun Young Lee , Sang Heon Lee , Nak Woong Eum
发明人： Jae-Jin Lee , Kyung Su Kim , Jun Young Lee , Sang Heon Lee , Nak Woong Eum
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： H04N19/436 , H04N19/176 , H04N19/184 , H04N19/44 , H04N19/61 , H04N19/91
摘要： An apparatus for decoding residual data based on a bit plane and a method thereof, capable of achieving a significant reduction in data traffic between a memory and a functional module in a parallel decoding system, include a variable length decoding module configured to generate residual data for each macroblock from a bit stream, divide the residual data into groups, and generate a bit plane regarding each of the groups, and a variable length decoding memory configured to store the bit plane generated from the variable length decoding module and store the residual data of the groups according to a value of the bit plane.
摘要翻译：一种用于解码基于位平面的残差数据的装置及其方法，其能够实现并行解码系统中的存储器与功能模块之间的数据流量的显着降低，包括：可变长度解码模块，被配置为产生残留数据，来自位流的每个宏块将残差数据分成组，并且生成关于每个组的位平面;以及可变长度解码存储器，被配置为存储从可变长度解码模块生成的位平面，并存储该组根据位平面的值。

47. 发明申请

US20130212594A1 METHOD OF OPTIMIZING PERFORMANCE OF HIERARCHICAL MULTI-CORE PROCESSOR AND MULTI-CORE PROCESSOR SYSTEM FOR PERFORMING THE METHOD 审中-公开
标题翻译：优化分层多核处理器性能的方法和多核处理器系统的执行方法
公开(公告)号：US20130212594A1
公开(公告)日：2013-08-15
申请号：US13617294
申请日：2012-09-14
申请人： Min Seok CHOI , Nak Woong Eum
发明人： Min Seok CHOI , Nak Woong Eum
IPC分类号： G06F9/50
CPC分类号： G06F9/5066 , Y02D10/22 , Y02D10/36
摘要： Disclosed is a multi-core processor, and more particularly, a method of optimizing performance of a multi-core processor having a hierarchical structure and a multi-core processor system for performing the method. To this end, the method of optimizing performance of a hierarchical multi-core processor including a plurality of kernel cores, each kernel core including a plurality of cores sharing a memory, the method includes calculating a correlation between a plurality of threads by a thread correlation managing module within a main processor; grouping the plurality of threads into two or more threads according to information on the calculated correlation by the main processor; and allocating each of the grouped threads within an equal group to each core within an equal kernel core of the hierarchical multi-core processor by a scheduler of the main processor.
摘要翻译：公开了一种多核处理器，更具体地，涉及一种优化具有层次结构的多核处理器和用于执行该方法的多核处理器系统的性能的方法。为此，包括多个内核核心的分级多核处理器的性能优化的方法，每个核心包括共享存储器的多个核，所述方法包括通过线程相关来计算多个线程之间的相关性主处理器内的管理模块; 根据关于由主处理器计算的相关性的信息，将多个线程分组成两个或更多个线程; 以及通过所述主处理器的调度器将所述分组线程中的每一个分配到所述分层多核处理器的相同内核核心内的相同组内的每个核心。

48. 发明授权

US08489818B2 Core cluster, energy scalable vector processing apparatus and method of vector processing including the same 有权
标题翻译：核心集群，能量可缩放矢量处理装置和包括其的矢量处理方法
公开(公告)号：US08489818B2
公开(公告)日：2013-07-16
申请号：US12841605
申请日：2010-07-22
申请人： Young Su Kwon , Moo Kyoung Chung , Nak Woong Eum
发明人： Young Su Kwon , Moo Kyoung Chung , Nak Woong Eum
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F1/3237 , G06F1/3225 , G06F1/3275 , G06F1/3287 , G06F12/0875 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： A core cluster includes a cache memory, a core, and a cluster cache controller. The cache memory stores and provides instructions and data. The core accesses the cache memory or a cache memory provided in an adjacent core cluster, and performs an operation. The cluster cache controller allows the core to access the cache memory when the core requests memory access. The cluster cache controller allows the core to access the cache memory provided in the adjacent core cluster when the core requests a clustering to the adjacent core cluster. The cluster cache controller allows a core provided in the adjacent core cluster to access the cache memory when the core receives a clustering request from the adjacent core cluster.
摘要翻译：核心集群包括高速缓存，核心和集群高速缓存控制器。高速缓存存储器并提供指令和数据。核心访问高速缓冲存储器或相邻核心群集中提供的缓存存储器，并执行操作。当核心请求存储器访问时，集群高速缓存控制器允许内核访问高速缓存。当核心请求聚簇到相邻核心群集时，群集高速缓存控制器允许核心访问相邻核心群集中提供的高速缓存存储器。当核心从相邻核心群集接收到聚类请求时，群集高速缓存控制器允许在相邻核心群集中提供的核心访问高速缓冲存储器。

49. 发明申请

US20120128075A1 APPARATUS FOR DECODING RESIDUAL DATA BASED ON BIT PLANE AND METHOD THEREOF 失效
标题翻译：用于根据位平面解码残留数据的装置及其方法
公开(公告)号：US20120128075A1
公开(公告)日：2012-05-24
申请号：US13226765
申请日：2011-09-07
申请人： Jae-Jin Lee , Kyung Su Kim , Jun Young Lee , Sang Heon Lee , Nak Woong Eum
发明人： Jae-Jin Lee , Kyung Su Kim , Jun Young Lee , Sang Heon Lee , Nak Woong Eum
IPC分类号： H04N7/26
CPC分类号： H04N19/436 , H04N19/176 , H04N19/184 , H04N19/44 , H04N19/61 , H04N19/91
摘要： An apparatus for decoding residual data based on a bit plane and a method thereof, capable of achieving a significant reduction in data traffic between a memory and a functional module in a parallel decoding system, include a variable length decoding module configured to generate residual data for each macroblock from a bit stream, divide the residual data into groups, and generate a bit plane regarding each of the groups, and a variable length decoding memory configured to store the bit plane generated from the variable length decoding module and store the residual data of the groups according to a value of the bit plane.
摘要翻译：一种用于解码基于位平面的残差数据的装置及其方法，其能够实现并行解码系统中的存储器与功能模块之间的数据流量的显着降低，包括：可变长度解码模块，被配置为产生残留数据，来自位流的每个宏块将残差数据分成组，并且生成关于每个组的位平面;以及可变长度解码存储器，被配置为存储从可变长度解码模块生成的位平面，并存储该组根据位平面的值。

50. 发明申请

US20100135362A1 FRAME SYNCHRONIZATION METHOD AND RECEIVER FOR COMMUNICATION MODEM USING THE SAME 失效
标题翻译：帧同步方法和接收机，用于通信调制解调器
公开(公告)号：US20100135362A1
公开(公告)日：2010-06-03
申请号：US12629014
申请日：2009-12-01
申请人： Ki Hyuk Park , Bon Tae Koo , Nak Woong Eum
发明人： Ki Hyuk Park , Bon Tae Koo , Nak Woong Eum
IPC分类号： H04B1/707
CPC分类号： H04B1/7075 , H04J3/0608
摘要： Disclosed are a frame synchronization method and a receiver for a communication modem using the same. The frame synchronization method includes performing a correlation operation between a reception data stream and a preamble to output a synchronous signal; and computing correlation values between spreading codes and a reception data stream synchronized with the synchronous signal, wherein a maximum value of the computed correlation values is compared with a preset threshold value, and the outputting of the synchronous signal is performed again when the maximum value is smaller than the preset threshold value.
摘要翻译：公开了一种帧同步方法和使用该帧同步方法的通信调制解调器的接收机。帧同步方法包括执行接收数据流与前同步码之间的相关运算以输出同步信号; 以及计算扩展码与与所述同步信号同步的接收数据流之间的相关值，其中将所计算的相关值的最大值与预设阈值进行比较，并且当所述最大值为小于预设阈值。

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